A Behavioral Synthesis Approach for Distributed Memory FPGA Architectures

Pal, Ashutosh; Balakrishnan, M.

doi:10.1109/fpl.2007.4380706

Cited by 2 publications

(2 citation statements)

References 6 publications

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“…Many studies have demonstrated that modern FPGA devices can implement an integrated controller and datapath architecture that either communicate with a monolithic memory or a banked or hierarchical memory organization [3], [4]. However, as modern FPGA devices become increasingly larger in size, the cost of global communication on-chip, both in delay and energy consumption, grows rapidly.…”

Section: Introductionmentioning

confidence: 99%

Improving memory performance in reconfigurable computing architecture through hardware-assisted dynamic graph

Bai

Alawad

Riera

et al. 2013

2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig)

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Being "memory-centric", the single-chip distributed logic-memory (DLM) architecture can significantly improve the overall performance and energy efficiency of many memoryintensive embedded applications, especially those that exhibit irregular array data access patterns at algorithmic level. However, implementing DLM architecture poses unique challenges to an FPGA designer in terms of 1) organizing and partitioning diverse on-chip memory resources, and 2) orchestrating effective data transmission between on-chip and off-chip memory. In this paper, we offer our solutions to both of these challenges. Specifically, 1) we propose a stochastic memory partitioning scheme based on the well-known simulated annealing algorithm. It obtains memory partitioning solutions that promote parallelized memory accesses by exploring large solution space; 2) we augment the proposed DLM architecture with a reconfigure hardware graph that can dynamically compute precedence relationship between memory partitions, thus effectively exploiting algorithmic level memory parallelism on a per-application basis.We evaluate the effectiveness of our approach (A3) against two other DLM architecture synthesizing methods: an algorithmiccentric reconfigurable computing architectures with a single monolithic memory (A1) and the heterogeneous distributed architectures synthesized according to [1] (A2). To make our comparison fair, in all three architectures, the data path remains the same while local memory architecture differs. For each of ten benchmark applications from SPEC2006 and MiBench [2], we break down the performance benefit of using A3 into two parts: the portion due to stochastic local memory partitioning and the portion due to the dynamic graph-based memory arbitration. All experiments have been conducted with a Virtex-5 (XCV5LX155T-2) FPGA. On average, our experimental results show that our proposed A3 architecture outperforms A2 and A1 by 34% and 250%, respectively. Within the performance improvement of A3 over A2, more than 70% improvement comes from the hardware graph-based memory scheduling.

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Section: Introductionmentioning

confidence: 99%

Improving memory performance in reconfigurable computing architecture through hardware-assisted dynamic graph

Bai

Alawad

Riera

et al. 2013

2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig)

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“…FPGAs have a large amount of memory distributed throughout the device. This memory neatly lends itself for tasks where distributed memory, close to the point of use, such as loop operations and array intensive operations [31]. By extension, we can use the embedded memory blocks to create the sets of registers used to set up and control the FPGA.…”

Section: Introductionmentioning

confidence: 99%

A distributed memory, local configuration technique for re-configurable logic designs

Beasley¹

2020

Preprint

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The use and location of memory in integrated circuits plays a key factor in their performance. Memory requires large physical area, access times limit overall system performance and connectivity can result in large fan-out. Modern FPGA systems and ASICs contain an area of memory used to set the operation of the device from a series of commands set by a host. Implementing these settings registers requires a level of care otherwise the resulting implementation can result in a number of large fan-out nets that consume valuable resources complicating the placement of timing critical pathways. This paper presents an architecture for implementing and programming these settings registers in a distributed method across an FPGA and how the presented architecture works in both clock-domain crossing and dynamic partial re-configuration applications. The design is compared to that of a 'global' settings register architecture. We implement the architectures using Intel FPGAs Quartus Prime software targeting an Intel FPGA Cyclone V. It is shown that the distributed memory architecture has a smaller resource cost (as small as 25% of the ALMs and 20% of the registers) compared to the global memory architectures.

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A Behavioral Synthesis Approach for Distributed Memory FPGA Architectures

Cited by 2 publications

References 6 publications

Improving memory performance in reconfigurable computing architecture through hardware-assisted dynamic graph

Improving memory performance in reconfigurable computing architecture through hardware-assisted dynamic graph

A distributed memory, local configuration technique for re-configurable logic designs

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