2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig) 2013
DOI: 10.1109/reconfig.2013.6732300
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Improving memory performance in reconfigurable computing architecture through hardware-assisted dynamic graph

Abstract: Being "memory-centric", the single-chip distributed logic-memory (DLM) architecture can significantly improve the overall performance and energy efficiency of many memoryintensive embedded applications, especially those that exhibit irregular array data access patterns at algorithmic level. However, implementing DLM architecture poses unique challenges to an FPGA designer in terms of 1) organizing and partitioning diverse on-chip memory resources, and 2) orchestrating effective data transmission between on-chi… Show more

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