Complementary Driving between 2D Heterostructures and Surface Functionalization for Surpassing Binary Logic Devices

Abstract

Recently, for overcoming the fundamental limits of conventional silicon technology, multivalued logic (MVL) circuits based on two-dimensional (2D) materials have received significant attention for reducing the power consumption and the complexity of integrated circuits. Compared with the conventional silicon complementary metal oxide semiconductor technology, new functional heterostructures comprising 2D materials can be readily implemented, owing to their unique inherent electrical properties. Furthermore, their process integration does not pose issues of lattice mismatch at junction interfaces. This facilitates the realization of new functional logic gate circuit configurations. However, the reported three-valued NOT gates (ternary inverters) based on 2D materials require stringent operating conditions and complex fabrication processes to obtain three distinct logic states. Herein, a general structure of MVL devices based on a simple series connection of 2D materials with partial surface functionalization is demonstrated. By arranging three 2D materials exhibiting p-type, ambipolar, and n-type conductivities, ternary inverter circuits can be established based on the complementary driving between 2D heterotransistors. This ternary inverter circuit can be further improved for quaternary inverter circuits by controlling the charge neutral point of partial ambipolar 2D materials using surface functionalization, which is an effective and nondestructive doping method for 2D materials.

Ferroelectric Field‐Effect‐Transistor Integrated with Ferroelectrics Heterostructure

“…The vdW heterostructure with a charge trap‐free interface can be implemented without lattice mismatch, owing to the dangling bond‐free surface nature. [ 29,30 ] The corresponding Raman peaks for each layer also indicate the existence of α ‐In 2 Se 3 , CIPS (Figure 1e), and h‐BN (Figure S1, Supporting Information) in the fabricated vdWHs.…”

Looking Beyond 0 and 1: Principles and Technology of Multi‐Valued Logic Devices

“…[ 55 ] Four logic states were also generated in inverters composed of two heterojunction NDT devices with N‐shaped transfer I – V curves. [ 65 ] Finally, a four‐state function was realized by using an NDT device with a Λ‐shaped I – V curve. In this MVL gate, binary inputs applied to the drain and gate terminals in different combinations were converted into a four‐state output.…”

“…[55] Four logic states were also generated in inverters composed of two heterojunction NDT devices with N-shaped transfer I-V curves. [65] Finally, a four-state function was realized by using an NDT device with a Λ-shaped I-V c) Reproduced with permission. [28] Copyright 2016, American Chemical Society.…”

Transistors and logic circuits enabled by 2D transition metal dichalcogenides: a state-of-the-art survey

“…Another strategy for establishing a ternary inverter and even a quaternary inverter can be demonstrated by introducing p-type, ambipolar and n-type TMD materials with appropriate threshold voltages. 140…”

“…Taking a step further, multivalued logic units are alternative candidates with great promise for superseding the integration density limitation of logic devices. 140 A theoretical study revealed that ternary and quaternary logic devices can replace binary logic devices with 36% and 50% fewer interconnecting lines, respectively. 141 In 2017, Huang et al constructed a tunable inverter composed of black phosphorus (BP) transistors in series with an n-MoS 2 FET with variable channel length, achieving a transition from a typical binary logic inverter to a tunable ternary inverter (Fig.…”