Transistors and logic circuits enabled by 2D transition metal dichalcogenides: a state-of-the-art survey

Qian, Fangsheng; Bu, Xiaobo; Wang, Junjie; Mao, Jing‐Yu; Han, Su‐Ting; Zhou, Ye

doi:10.1039/d2tc00964a

Cited by 12 publications

(5 citation statements)

References 202 publications

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“…Moreover, they suffer from non‐ideal structure termination with rough surfaces and unavoidable surface/interface dangling bonds, which lead to interface states (Shockley–Tamm states) that can strongly scatter the charge carriers. [ 55 ] As a result, a substantial degradation of µ is observed with decreasing body thickness, with µ proportional to the sixth power of the thickness in the sub‐5 nm regime. [ 56 ] Besides, the emerging trillion‐level IoT demand poses a significant challenge to the cost and production capacity of silicon CMOS.…”

Section: Device Structures Metrics and Superioritymentioning

confidence: 99%

Thin‐Film Transistors for Integrated Circuits: Fundamentals and Recent Progress

Yan,

Wang,

Yan

et al. 2023

Adv Funct Materials

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High‐performance thin‐film transistors (TFTs) integrated circuits (ICs) have become increasingly necessary to meet the emerging demands such as healthcare, edge computing, and the Internet of Things, etc. This article aims to point out the potential development trends and bottlenecks of TFT ICs, enhancing their performance in terms of electronic performance, stability, consistency, CMOS design, and manufacturing capability. Basic device structures and overall metrics of TFT ICs are explored, as well as their superiority compared to silicon‐based ultrathin chips. Hydrogenated amorphous silicon, low‐temperature polycrystalline silicon, and amorphous oxide semiconductors are widely used in displays due to their ability to be deposited on large areas at low processing temperatures and low cost, and are validated in many prototypes for TFT ICs. Their conduction mechanisms, process flows, performance evaluation, and recent advances are comprehensively viewed. In addition, the potential of emerging low‐dimensional materials as next‐generation channel materials is discussed, along with their limitations and progress in this field. Finally, the major challenges in manufacturing high‐performance TFT ICs and future perspectives are summarized.

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Section: Device Structures Metrics and Superioritymentioning

confidence: 99%

Thin‐Film Transistors for Integrated Circuits: Fundamentals and Recent Progress

Yan,

Wang,

Yan

et al. 2023

Adv Funct Materials

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“…When lithographically patterned intraflake devices on mechanically exfoliated MoS 2 are concerned, combining those high-performance thin film transistors, numerous circuit elements have also been reported in the literature. ,− Notably, even 1 bit microprocessors have been demonstrated as early as 2017 . Nonetheless, the roadblock in upscaling such circuit elements has hindered their widespread realization for unconventional or flexible electronic applications.…”

Section: Introductionmentioning

confidence: 99%

Inkjet-Printed, High-Performance MoS₂ Transistors and Unipolar Logic Electronics

Mondal,

Prakasan,

Kolluru

et al. 2024

ACS Appl. Mater. Interfaces

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semiconductor field-effect film transistors combine large carrier mobility with mechanical flexibility and therefore can be ideally suitable for wearable electronics or at the sensor interfaces of smart sensor systems. However, such applications require large-area solution processing as opposed to single-flake devices, where the critical challenge to overcome is the high interflake resistance values. In this report, using a narrow-channel, near-vertical transport device architecture, we have fabricated inkjet-printed sub-20 nm channel electrolytegated transistors with predominantly intraflake carrier transport. Therefore, the electronics transport in these transistors is not dominated by the high interflake resistance, and the intraflake material properties including doping density, defect concentration, contact resistance, and threshold voltage modulation can be examined and optimized independently to achieve a current density as high as 280 μA•μm −1 . In addition, through the passivation of the sulfur vacancies with a tailored surface treatment, we demonstrate an impressive On−Off current ratio exceeding 1 × 10 7 , complemented by a low subthreshold swing of 100 mV•decade −1 . Next, exploiting these high-performance transistors, unipolar depletion-load-type inverters have been fabricated that show a maximum gain of 31. Furthermore, we have realized NAND, NOR, and OR gates, demonstrating their seamless operation at a frequency of 1 kHz. Therefore, this work represents an important step forward to realize electronic circuits based on printed 2D thin film transistors.

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“…GrO buffer layer can only be utilized for application that can tolerate its contribution to the gate capacitance, for which there is still a large array of logic gates and integrated circuits envisioned 27 . Nonetheless, the concept proposed in this paper i.e., a Graphene-based nucleation-/ passivation layer can be tailored to any type of functionalization required for precursor gases to react with, enabling alternative material growths (other than dielectrics) depending on the application.…”

Section: Introductionmentioning

confidence: 99%

Enabling high quality dielectric passivation on Monolayer WS2 using a sacrificial Graphene Oxide template

Wyndaele¹,

Marneffe²,

Sergeant³

et al. 2023

Preprint

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Two-dimensional transition metal dichalcogenides (2D TMDC’s) hold a wide variety of applications, among which microelectronic devices. However, various challenges hinder their integration e.g., good dielectric deposition on the 2D TMDC surface. In this work, a sacrificial, Graphene oxide (GrO)-based buffer layer is used to 1) serve as a passivation layer, protecting the underlying 2D TMDC (WS2) and 2) act as a nucleation layer, enabling uniform dielectric (HfO2) growth. A Graphene layer is transferred on monolayer WS2, after which polymeric transfer residues are cleaned via a combination of wet- and dry treatments. Next, the cleaned Graphene is functionalized via a dry UV/O3 oxidative exposure. It is shown that the Graphene UV/O3 oxidation rate is substrate dependent and proceeds slower when Graphene is transferred on WS2 compared to SiO2, due to UV-light induced, ultrafast charge transfer between the Graphene and WS2 monolayer. The carbon-oxygen groups formed on Graphene’s basal plane act as nucleation sites in a subsequent HfO2 atomic layer deposition process, achieving a smoother dielectric layer in comparison to direct deposition on bare WS2. Finally, by means of a GrO FET device, it is shown that the GrO nucleation layer does not compromise the device transport characteristics i.e., will not give rise to significant leakage currents in a 2D heterostack device.

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Transistors and logic circuits enabled by 2D transition metal dichalcogenides: a state-of-the-art survey

Abstract: Two-dimensional transition metal dichalcogenides (TMDs) have witnessed scientific research interests in recent years thanks to the absence of dangling bonds, ultrathin-body and two-surface-channel essences, giving rise to an enhanced electrostatic...

Cited by 12 publications

References 202 publications

Thin‐Film Transistors for Integrated Circuits: Fundamentals and Recent Progress

Thin‐Film Transistors for Integrated Circuits: Fundamentals and Recent Progress

Inkjet-Printed, High-Performance MoS₂ Transistors and Unipolar Logic Electronics

Enabling high quality dielectric passivation on Monolayer WS2 using a sacrificial Graphene Oxide template

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Transistors and logic circuits enabled by 2D transition metal dichalcogenides: a state-of-the-art survey

Abstract: Two-dimensional transition metal dichalcogenides (TMDs) have witnessed scientific research interests in recent years thanks to the absence of dangling bonds, ultrathin-body and two-surface-channel essences, giving rise to an enhanced electrostatic...

Cited by 12 publications

References 202 publications

Thin‐Film Transistors for Integrated Circuits: Fundamentals and Recent Progress

Thin‐Film Transistors for Integrated Circuits: Fundamentals and Recent Progress

Inkjet-Printed, High-Performance MoS2 Transistors and Unipolar Logic Electronics

Enabling high quality dielectric passivation on Monolayer WS2 using a sacrificial Graphene Oxide template

Contact Info

Product

Resources

About

Inkjet-Printed, High-Performance MoS₂ Transistors and Unipolar Logic Electronics