Complementary Unipolar WS₂ Field‐Effect Transistors Using Fermi‐Level Depinning Layers

Abstract

In this study, a 20 cycle atomic layer-deposited (ALD) TiO 2 dielectric interfacial layer was inserted between WS 2 and other metals (Ti and Pd) to lower the Schottky barrier height through a mechanism such as Fermi-level depinning as in a silicon device. In addition to dramatically reducing contact resistance, unipolar transfer characteristics could be achieved in WS 2 FETs by using a TiO 2 dielectric interfacial layer with both low and high work function metal-WS 2 contact systems (Ti-WS 2 and Pd-WS 2 , respectively).Figure 1 a shows the schematic of a back-gate WS 2 FET with a 20 cycle ALD TiO 2 interfacial layer. The channel length and width are ≈3 and ≈20 µm, respectively. A lattice constant of 0.65 nm for the WS 2 was confi rmed as shown in a representative high resolution transmission electron microscopy (HRTEM) image of the metal-TiO 2 -WS 2 stack (Figure 1 b). TiO 2 thickness ≈2.7 nm is expected based on the deposition rate of 0.135 nm per cycle. The fi gure inset is an electron diffraction pattern obtained from a Ti-TiO 2 -WS 2 stack structure. Raman spectra for bi-and multilayer WS 2 are shown in Figure 1 c, and corresponding optical images are shown in Figure 1 d. The Raman spectra for WS 2 include two modes: the E 1 2g mode, which corresponds to the in-plane vibrational motion of atoms, and the A 1g mode, which is attributed to the out-of-plane vibrational motion of atoms. The thickness of the WS 2 layer can be extracted from the shift in the wavenumber. As the thickness increases, the wavenumber between E 1 2g and A 1g and the absolute intensity increase, while the intensity ratio of E 1 2g to A 1g decreases. [ 43 ] Figure 2 a shows the transfer characteristics ( I DS -V BG ) of WS 2 FETs with a Ti electrode (work function ≈4.3 eV). The drain bias was increased from 0.1 to 0.5 V in 0.1 V steps. The transfer characteristics showed bipolar behavior with a hole current for the negative gate bias region and electron current for the positive gate bias region. This is typical behavior for Schottky barrier FETs with a midgap-like contact metal. The effective position of the Fermi level appears to have shifted to the near midgap of WS 2 , forming a high Schottky barrier for both electrons and holes as shown in Figure 2 e. With a metal-semiconductor contact, when the effective workfunction of a metal is shifted by extrinsic mechanisms, the barrier height can be defi ned considering the Fermi-level pinning factor as shown in the equation below 1 B,n 0 gs M s gs 0where B,n 0 Φ is the barrier height, M φ is the work function of the metal electrode, s χ is the electron affi nity of the semiconductor, gs γ is parameter for the gap states, and 0 φ is a charge neutrality position. [ 44 ] The shift in the location of Fermi level can be caused by many factors such as surface states, metal-induced gap states (MIGS), defect states, or disorder-induced gap states, etc. [36][37][38]45,46 ] Recently, 2D transition metal dichalcogenides (TMDs) have attracted intense research interests due to their unique electrical, optica...

Schottky Contact in Monolayer WS2 Field‐Effect Transistors

“…However, because of the extensive existence of the metal induced gap states (MIGS), the Fermi level pinning effect is evident, and the SBH cannot be simply determined from the difference between the Fermi level of the metal and the conduction band minimum (CBM) or valence band maximum (VBM) of the semiconductor. Experimentally, similar lateral electron Schottky barrier heights (SBHs) have been measured in FETs for Ti and Pd electrodes with the value of 0.24 and 0.23 eV, respectively, despite of a large difference in the work function between Ti and Pd . The hole SBHs in the periodic interface systems between ML WS 2 and Sc, Al, Cr, Ru, Co, Ni, Pt has been calculated but only in the vertical direction .…”

“…Because the traditional substitute doping method is hard to realize in 2DSC FETs, contacting metals in a direct way becomes a commonly used way to inject carriers into the 2DSCs . Experimentally, Ni, Ti, Cr, Au, Pd, and graphene have been adopted as electrodes in WS 2 FETs . There are two kinds of interfaces in the FET configuration, as labeled in Figure : the one is the vertical interface (interface B) between metal and the underneath ML WS 2 , and the other is the lateral interface (interface D) between the electrode ML WS 2 and the channel ML WS 2 .…”

Enhanced Performance of MoS2 Photodetectors by Inserting an ALD‐Processed TiO2 Interlayer

“…In the bare MoS 2 device, drain current ( I D ) increase is small and unstable, creating the current at the level of leakage until the V G reaches −30 V. However, the TiO 2 /MoS 2 device exhibits a linear increase of the drain current as a function of the source‐drain voltages ( V SD ). The nonordered defective interface (Figure e) causes a slow and small I – V characteristic (Figure a) due to the contact resistance ( R C ) . Figure c shows that the transfer characteristics of both bare MoS 2 and TiO 2 /MoS 2 devices introduce a typical n‐type depletion‐mode behavior.…”

“…In this work, we address the interface issue by inserting twenty atomic layer deposition (ALD) cycles of TiO 2 into the interface between MoS 2 and a metal electrode. Although this TiO 2 interlayer concept was theoretically studied and practically utilized in field effect transistor devices, its positive effect on the performance of MoS 2 photodetectors has yet to be explored. Here, the enhanced photoresponsivity and response‐recovery speed of the MoS 2 ‐based photodetectors with the TiO 2 interlayer are statistically demonstrated.…”

Enhanced Photoresponse of WS2 Photodetectors through Interfacial Defect Engineering Using a TiO2 Interlayer

“…In this case, hole conductivity is suppressed and the Fermi energy level is depinned. 35,43 Therefore, the TiO Figure S3 in Supporting Information). In the bare WS 2 device, photocurrent (I ph ) gradually increased and the recovery was incomplete even after 5 min, as shown in Figure 3b.…”