Complete nanowire crossbar framework optimized for the multi-spacer patterning technique

Ben-Jamaa, M. Haykel; Cerofolini, G. F.; Leblebici, Yusuf; Micheli, Giovanni De

doi:10.1145/1629395.1629398

Cited by 8 publications

(3 citation statements)

References 15 publications

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“…13. This process has been reported for the construction of dense poly-SiNW crossbar arrays [40]. A small crossbar with one upper poly-SiNW and four lower poly-SiNW is shown in Fig.…”

Section: B Poly-si Nanowire Fetsmentioning

confidence: 94%

Multiterminal Memristive Nanowire Devices for Logic and Memory Applications: A Review

2012

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| Memristive devices have the potential for a complete renewal of the electron devices landscape, including memory, logic, and sensing applications. This is especially true when considering that the memristive functionality is not limited to two-terminal devices, whose practical realization has been demonstrated within a broad range of different technologies. For electron devices, the memristive functionality can be generally attributed to a material state modification, whose dynamics can be engineered to target a specific application. In this review paper, we show that trap charging dynamics can explain some of the memristive effects previously reported for Schottky-barrier field-effect Si nanowire transistors (SB SiNW FETs). Moreover, the SB SiNW FETs do show additional memristive functionality due to trap charging at the metal/ semiconductor surface. The combination of these two memristive effects into multiterminal metal-oxide-semiconductor field-effect transistor (MOSFET) devices gives rise to new opportunities for both memory and logic applications as well as new sensors based on the physical mechanism that originate memristance. In the special case of four-terminal memristive Si nanowire devices, which are presented for the first time in this paper, enhanced functionality is demonstrated. Finally, the multiterminal memristive devices presented here have the potential of a very high integration density, and they are suitable for hybrid complementary metal-oxide-semiconductor (CMOS) cofabrication with a CMOS-compatible process.

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“…13. This process has been reported for the construction of dense poly-SiNW crossbar arrays [40]. A small crossbar with one upper poly-SiNW and four lower poly-SiNW is shown in Fig.…”

Section: B Poly-si Nanowire Fetsmentioning

confidence: 94%

Multiterminal Memristive Nanowire Devices for Logic and Memory Applications: A Review

2012

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“…The SNAP technique has allowed the preparation of contact masks with p = 16 nm (and thus with the linear density of 6×10 5 cm −1 ) [7] and SNAP masks were used to demonstrate the feasibility of crossbars hosting reprogrammable molecules as memory elements at a bit density of 10 11 cm −2 [8]. The MSPT, instead, has succeeded in the preparation of wires with w = 7 nm [13] and used for the demonstration of crossbar memories with bit density of the order of 10 10 cm −2 [22].…”

Section: Non-lithographic Techniques On the Nanoscalementioning

confidence: 99%

Crossbar architecture for tera-scale integration

Cerofolini

Ferri²,

Romano

et al. 2011

Semicond. Sci. Technol.

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As far as the fabrication of ultradense crossbars is related to correspondingly dense wire arrays, the crossbar route to tera-scale integration depends on the availability of preparation techniques for wire arrays with density of 10 6 cm −1 or more. For a planar arrangement this density implies a pitch of 10 nm or less, beyond the current possibility and close to the theoretical limit, assuming for the cross-point a minimum area of 10 nm 2 . Further increase of density can only be achieved organizing the nanowires in a three-dimensional fashion. This paper describes a planar top-down process for the preparation of vertically arranged poly-silicon nanowires. The technique is expected to allow the production of wire arrays with linear density (projected on the surface) larger than those achievable with any other proposed top-down processes. Used for the fabrication of the bottom wire array of crossbars, this process should allow an eventual cross-point density of the order of 10 12 cm −2 , thus being a candidate technology for tera-scale integration.

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“…Moreover, silicon is particularly interesting for molecular electronics because it can be terminated with organic moieties carrying wanted electrical properties (like reprogrammable molecules with two well separated conduction states) bonded to the silicon via environmentally robust Si-C bonds [15]. The MSPTs have succeeded in the preparation of silicon wire arrays with pitch p on the 10-nm length scale [16][17][18][19][20][21][22][23][24]: nanowires with width of 7 nm and arrays with p = 35 nm have actually been reported [17,18], whereas the most dense crossbar hitherto produced had a bit density of the order of 10 10 cm −2 [25]. The size to which a nanowire can be scaled down is manifestly limited by the appearance of quantum size effects.…”

Section: Silicon Nanowiresmentioning

confidence: 99%

Terascale integration via a redesign of the crossbar based on a vertical arrangement of poly-Si nanowires

Cerofolini

Ferri²,

Romano

et al. 2010

Semicond. Sci. Technol.

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The race of integrated-circuit technology toward high bit density has already brought to transistor densities of the order of 10 9 cm −2 , yet keeping conventional circuit layouts. Crossbar structures are widely believed to meet the requirements of high bit density along with sustainable interconnection complexity avoiding the dramatic cost increase of the manufacturing facilities required by advanced lithography. In this work we demonstrate the possibility of producing poly-Si nanowires preserving bulk electrical properties and nonetheless so dense as to allow cross-point density in excess of 10 11 cm −2 . This result could be achieved by organizing silicon nanowires in nearly vertical arrays.

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Complete nanowire crossbar framework optimized for the multi-spacer patterning technique

Cited by 8 publications

References 15 publications

Multiterminal Memristive Nanowire Devices for Logic and Memory Applications: A Review

Multiterminal Memristive Nanowire Devices for Logic and Memory Applications: A Review

Crossbar architecture for tera-scale integration

Terascale integration via a redesign of the crossbar based on a vertical arrangement of poly-Si nanowires

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