Composite Cores: Pushing Heterogeneity Into a Core

Abstract

Heterogeneous multicore systems-comprised of multiple cores with varying capabilities, performance, and energy characteristicshave emerged as a promising approach to increasing energy efficiency. Such systems reduce energy consumption by identifying phase changes in an application and migrating execution to the most efficient core that meets its current performance requirements. However, due to the overhead of switching between cores, migration opportunities are limited to coarse-grained phases (hundreds of millions of instructions), reducing the potential to exploit energy efficient cores.We propose Composite Cores, an architecture that reduces switching overheads by bringing the notion of heterogeneity within a single core. The proposed architecture pairs big and little compute µEngines that together can achieve high performance and energy efficiency. By sharing much of the architectural state between the µEngines, the switching overhead can be reduced to near zero, enabling fine-grained switching and increasing the opportunities to utilize the little µEngine without sacrificing performance. An intelligent controller switches between the µEngines to maximize energy efficiency while constraining performance loss to a configurable bound. We evaluate Composite Cores using cycle accurate microarchitectural simulations and a detailed power model. Results show that, on average, the controller is able to map 25% of the execution to the little µEngine, achieving an 18% energy savings while limiting performance loss to 5%.

The heterogeneous block architecture

“…Our first observation is that applications have fine-grained heterogeneity. Prior work has observed heterogeneity at a coarse granularity: for example, programs have memory and compute phases, and such phases can be exploited by migrating a thread to "big" cores for compute-intensive phases and "little" cores for memoryintensive phases [56,35]. However, at a finer granularity (of tens to hundreds of instructions), adjacent blocks of code often have different properties as well (as we will show).…”

“…The clusters have equivalent scheduler size and issue width as the block execution backends in the HBA core. We also compare to a coarse-grained heterogeneous design that combines an out-of-order and an in-order core [35]. To be fair in our comparisons, we idealized the controller we model for this coarse-grained design, which provides an upper bound on efficiency and performance relative to the real controller-based mechanism of [35].…”

“…We also compare to a coarse-grained heterogeneous design that combines an out-of-order and an in-order core [35]. To be fair in our comparisons, we idealized the controller we model for this coarse-grained design, which provides an upper bound on efficiency and performance relative to the real controller-based mechanism of [35]. To do so, we first run each benchmark on 4-wide OoO and 2-wide in-order cores and record statistics separately for each 1K-instruction epoch, then examine each epoch and combine the simulation results post-mortem.…”

“…Extensive evaluations of our core design in comparison to an out-of-order core, a clustered-microarchitecture core [17], and a state-of-the-art coarse-grained heterogeneous core [35] demonstrate higher energy efficiency than all previous designs across a variety of workloads. Our design reduces average core power by 36.4% with 1% performance degradation over the out-of-order baseline.…”

“…To exploit this diversity, past works proposed core-level heterogeneity. These heterogeneous designs either combine multiple separate cores (e.g., [29,22,3,20,53,7,12,26,4,56]), or else combine an inorder pipeline and out-of-order pipeline with a shared frontend in a single core [35]. Past works demonstrate energy-efficiency improvements with usually small impact to performance.…”