Composition control and ferroelectric properties of sidewalls in integrated three-dimensional SrBi2Ta2O9-based ferroelectric capacitors

Abstract

The difficult scaling of ferroelectric random access memories with the complementary metal-oxide semiconductor technology roadmap requires integration of three-dimensional (3D) ferroelectric capacitors (FeCAP’s). In this work the unusual electrical behavior of 3D FeCAP sidewalls was studied by comparing the electrical properties of two-dimensional and 3D integrated FeCAP structures. We evidenced composition variations of the SrBi2Ta2O9 (SBT) film in the sidewalls with marked bismuth segregation during metal-organic chemical-vapor deposition (MOCVD) of the SBT film. The segregation was reduced after decreasing the deposition temperature from 440°C, whereby the Bi-rich phase in the sidewalls does not contribute to polarization, down to 405°C, whereby sidewall SBT contributes to polarization. After further optimization of the MOCVD conditions at 405°C, the segregation is minimized and the ferroelectric contribution of the sidewall SBT is almost the same as the contribution of the planar SBT. As a result, 3D FeCAP’s integrated up to metal interconnection exhibit a remnant polarization Pr∼7.5μC∕cm2.

Morphological Control of Polar Orientation in Single-Crystal Ferroelectric Nanowires

“…10 An alternative scheme is to use ferroelectric films as the gate in field effect transistors, 11,12 but these suffer from retention loss (diminishing stored charge) due to the need to ground the gate during read operations. The work at IMEC 13 and the Samsung-Tokyo Institute of Technology collaboration 14 has resulted in some commercial deviceworthy parts, but at present there is no model for and little understanding of the nanodomain configurations adopted in such 3D ferroelectric devices. This is of great importance as the switching speed and operating device voltages depend upon the widths and geometries of the ferroelectric nanodomains.…”

Scaling potential of pin-type 3-D SBT ferroelectric capacitors integrated in 0.18μm CMOS technology

“…4), which is much less observed for 2-D capacitors. For 0.35 lm 3-D capacitors, similar increase was observed after fatigue, and could be attributed to a wakeup (poling) effect in the SBT sidewall material [4]. We believe that in as-prepared SBT capacitors, some ferroelectric domains are pinned by localized space charges in the sidewalls, and that this pinning is weak enough to be gradually removed under polarization reversal, resulting in a wake-up effect of spontaneous polarization after cycling.…”

“…This is lower than what could be geometrically expected, as the area gain from 2-D to 3-D FeCAP is nearly 100%, but in agreement with 0.35 lm results. The limited sidewall contribution may be explained by different SBT material composition at the sidewalls [4] while also mechanical stress effects may play a role as a change in lattice parameters has been observed [5]. However, despite the incomplete sidewall contribution to the polarization, 2P r $ 20 lC/cm 2 is achievable for 3-D capacitor arrays.…”

Enhanced oxidation of TiAlN barriers integrated in three-dimensional ferroelectric capacitor structures

“…However, despite the clear advantage that SBT grown at 440°C exhibits with a higher P r value, the larger TiAlN oxidation length ͑see above͒ makes them more critical to integrate. Furthermore, Goux et al 16 have shown that the increase of deposition temperature results in a larger leakage current density through the ferroelectric film and subsequently to lower reliability performances.…”

“…16 The maximum oxidation times were selected based on the criteria that W plugs are not oxidized assuring that the system is mechanically stable during the experiments.…”