Increasing system complexity, time to market and development costs reduction place higher demands on engineering processes. Formal models play an important role here because they enable the use of various model-based analyses and early integration techniques and tools. Engineering processes based on formal models are able to cope with complexity. They also support time to market and development costs reduction. Moreover, application of supervisory control synthesis in the development of control systems can speed up the process considerably. This paper discusses the integration of recently developed supervisor synthesis techniques and tools in engineering processes. To illustrate this approach, examples of industrial cases are presented, where supervisors synthesized have successfully been implemented and integrated in existing resource control platforms.
IntroductionIn current industrial practice, it is very difficult to deal with high-tech multidisciplinary system development due to system complexity, market pressure, and resource limitations. To overcome the difficulties, various kinds of models are used increasingly often in the development process. Specifically, formal and executable models built and employed in the design phase can be used to assess functional correctness and performance of component designs and overall system design. Formal verification, in particular model checking [3], is employed when a high degree of confidence in functional correctness of a design is required. To assess design performance, one