Comprehensive analysis of retention characteristics in 3-D NAND flash memory cells with tube-type poly-Si channel structure

Kang, Hyo; Choi, Nagyong; Joe, Sung-Min; Seo, Ji Hun; Choi, Eun-Seok; Park, Sung-Kye; Park, Byung‐Gook; Lee, Jong-Ho

doi:10.1109/vlsit.2015.7223670

Cited by 57 publications

(31 citation statements)

References 2 publications

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“…The initiation and magnitude of fast-drift co-depend on certain design parameters and the underlying environmental conditions. While recent works have acknowledged the presence of fast-drive in CT-flash 3D NAND [9,16,22,27,29], to the best of our knowledge, Reference [7] remains the only publicly available work reporting the detailed behavior of fast-drift phenomenon in the CT-flash cells. Motivated by their empirical data, we analytically characterized the relation between fast-drift and the parameters that critical affect it.…”

Section: Analytic Modelmentioning

confidence: 99%

“…Also, due to unavailability of 3D NAND chips (i.e., not the packaged SSDs, since they come with built-in proprietory counter-measures), we are yet to compare our results with empirical data. However, we encourage the interested reader to go over [7,9,16,21,22,[27][28][29], as they can provide further details regarding how each component of our model impacts fast-drift.…”

Section: Limitationsmentioning

confidence: 99%

“…Figure 1(a) presents the impact of such retention errors in terms of bit error rates (BER) in 3D NAND (CT-flash) normalized to that in 2D NAND (FG-flash). In this figure, the 2D NAND curve represents the well-known trend for FG-Flash devices [35], while the 3D NAND data are derived using our proposed analytic model for similar process technology and parameters and verified against available data [7,9,16]. One can notice from the figure that while 2D NAND starts to suffer from high BER only near the end of its retention period (∼10 years), 3D NAND can experience around 70% of the peak BER only months after a program.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

ReveNAND

Shihab¹,

Zhang

Kandemir

2018

ACM Trans. Archit. Code Optim.

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The paradigm shift from planar (two dimensional (2D)) to vertical (three-dimensional (3D)) models has placed the NAND flash technology on the verge of a design evolution that can handle the demands of next-generation storage applications. However, it also introduces challenges that may obstruct the realization of such 3D NAND flash. Specifically, we observed that the fast threshold drift (fast-drift) in a charge-trap flash-based 3D NAND cell can make it lose a critical fraction of the stored charge relatively soon after programming and generate errors. In this work, we first present an elastic read reference (V Ref) scheme (ERR) for reducing such errors in ReveNAND-our fast-drift aware 3D NAND design. To address the inherent limitation of the adaptive V Ref , we introduce a new intra-block page organization (hitch-hike) that can enable stronger error correction for the error-prone pages. In addition, we propose a novel reinforcement-learning-based smart data refill scheme (iRefill) to counter the impact of fast-drift with minimum performance and hardware overhead. Finally, we present the first analytic model to characterize fast-drift and evaluate its system-level impact. Our results show that, compared to conventional 3D NAND design, our ReveNAND can reduce fast-drift errors by 87%, on average, and can lower the ECC latency and energy overheads by 13× and 10×, respectively.

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Section: Analytic Modelmentioning

confidence: 99%

Section: Limitationsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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ReveNAND

Shihab¹,

Zhang

Kandemir

2018

ACM Trans. Archit. Code Optim.

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“…The retention properties of charge-trap based planar devices have been extensively investigated as a function of temperature and bias [300], pointing out the roles of vertical charge loss through the tunnel oxide and lateral charge migration in the nitride [301][302][303][304], which also reduces the stored charge located above the channel region, that determines V T . In 3D devices, the importance of such effects is shown in Figure 37, where lateral diffusion along the nitride is modulated by the state of adjacent cells [305]: having all cells programmed decreases the concentration gradient, slowing down diffusion and reducing the V T shift. Similar results obtained via simulations were also presented in [306][307][308] and, changing the device size, in [309].…”

Section: Retentionmentioning

confidence: 99%

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

2017

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Abstract:We review the state-of-the-art in the understanding of planar NAND Flash memory reliability and discuss how the recent move to three-dimensional (3D) devices has affected this field. Particular emphasis is placed on mechanisms developing along the lifetime of the memory array, as opposed to time-zero or technological issues, and the viewpoint is focused on the understanding of the root causes. The impressive amount of published work demonstrates that Flash reliability is a complex yet well-understood field, where nonetheless tighter and tighter constraints are set by device scaling. Three-dimensional NAND have offset the traditional scaling scenario, leading to an improvement in performance and reliability while raising new issues to be dealt with, determined by the newer and more complex cell and array architectures as well as operation modes. A thorough understanding of the complex phenomena involved in the operation and reliability of NAND cells remains vital for the development of future technology nodes.

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“…As the technology node scales down, NAND Flash storage density increases with unavoidable reliability degradation. The main reliability issues of NAND Flash consist of data retention [1], program disturb [2], cell to cell interference [3], read disturb [4] et al Data retention error is the dominant error source among these reliability issues. One of the effective ways to deal with data retention error is to apply ECC (error correction code) [5].…”

Section: Introductionmentioning

confidence: 99%

Word line interference based data recovery technique for 3D NAND Flash

Huo

Liu

Cao

et al. 2018

IEICE Electron. Express

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When the NAND Flash memory is used beyond specific retention time, data stored in NAND Flash memory may not be read out correctly due to retention error. In this paper, a word line interference (WI) based data recovery technique is proposed to recover retention-failed data. By using WI, a large amount of electrons can be re-injected into retention-failed cells with one program operation. To improve recovery efficiency and recover retention error in a block, an iterated WI recovery algorithm which combines WI and previously reported DRRP technique is proposed. Experiment results show that WI recovery technique gains a higher recovery efficiency compared with DRRP technique.

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Comprehensive analysis of retention characteristics in 3-D NAND flash memory cells with tube-type poly-Si channel structure

Cited by 57 publications

References 2 publications

ReveNAND

ReveNAND

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

Word line interference based data recovery technique for 3D NAND Flash

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