Comprehensive Methodology for ReRAM and Selector Design Guideline of Cross-point Array

Abstract

In this research, an one selector-one ReRAM (1S1R) cross-point array of a multi-level cell (MLC) was demonstrated and investigated. To expand high-density feasibility of cross-point array, MLC pulse writing and reading operations were assessed with parasitic line resistances and capacitances using Matlab and HSPICE simulations. We observed a switching energy is an important parameter for MLC in actual cross-point array in the operating point of view. In addition, not only ReRAM but also selector characteristics are highly important in the device point of view. Therefore, this study serves power efficient guidelines for 1S1R devices and operating schemes of cross-point array.

SneakPath compensation circuit for programming and read operations in RRAM-based CrossPoint architectures

“…In a large crossbar array and due to SP, reading different resistance level on the same bit-cell can be difficult to operate without increasing significantly the read consumption [16]. The proposed SP compensation circuit can be advantageously used to increase the read precision.…”

Exploration of selector characteristic based on electron tunneling for RRAM array application

“…It possesses the potential for high-density storage benefiting from its high scalability, fast switching speed and low power consumption [1]. The RRAM element based on crossbar array can attain feature size of 4F 2 (F is the line width) or even less when multilevel is realized [2]. Nonetheless, as the array is constructed by pure RRAM element leakage current is inevitable.…”