Comprehensive multiprocessor cache miss rate generation using multivariate models

Abstract

This article presents a technique for taking a sparse set of cache simulation data and fitting a multivariate model to fill in the missing points over a broad region of cache configurations. We extend previous work by its applicability to multiple miss rate components and its ability to model a wide range of cache parameters, including size, associativity and sharing. Miss rate models are useful for broad design exploration in which many cache configurations cannot be simulated directly due to limitations of trace collection setups or available resources. We show the effectiveness of the technique by applying it to two commercial workloads and presenting miss rate data for a broad design space with cache size, associativity, sharing and number of processors as variables. The fitted data match the simulation data very well. The various curves show how a miss rate model is useful for not only estimating the performance of specific configurations, but also for providing insight into miss rate trends. Furthermore, this modeling methodology is robust in the presence of corrupted simulation data and variations in simulation data from multiple sources.

Modelling the Performance of the Gaussian Chemistry Code on x86 Architectures

“…Using a sparse set of trace based cache simulations, Gluhovsky and O'Krafka [9] build a multivariate model of multiple cache miss rate components. This can then be used to extrapolate for other hypothetical system configurations.…”

A case study in top-down performance estimation for a large-scale parallel application

“…We followed the approach of [8] using the algorithm in [9] to carry out statistical extrapolation using the small system data available from the memory hierarchy simulator. These estimated miss rates are used as inputs to the system model as described in Section 5.…”

Memory subsystem simulation in software TLM/T models

“…In behavioral-level simulation [1,5,8,12,13,15,21], memory accesses that are generated when software is compiled are not visible in a high-level programs. In [6,7,9,14,17,20], memory subsystem is not accurate simulated. In instruction-by-instruction [2,3,10,16,19,22], simulation is inefficient and does not provide sufficient speed for system-level DSE.…”

“…Analytical method in [20] only works on parallel algorithms with regular data access patterns and does not work on regular programs in general. Multivariate models [7] use statistics to estimate memory subsystem performance based on the results from a number of simulations. But such method has not been shown accurate.…”