This article presents a technique for taking a sparse set of cache simulation data and fitting a multivariate model to fill in the missing points over a broad region of cache configurations. We extend previous work by its applicability to multiple miss rate components and its ability to model a wide range of cache parameters, including size, associativity and sharing. Miss rate models are useful for broad design exploration in which many cache configurations cannot be simulated directly due to limitations of trace collection setups or available resources. We show the effectiveness of the technique by applying it to two commercial workloads and presenting miss rate data for a broad design space with cache size, associativity, sharing and number of processors as variables. The fitted data match the simulation data very well. The various curves show how a miss rate model is useful for not only estimating the performance of specific configurations, but also for providing insight into miss rate trends. Furthermore, this modeling methodology is robust in the presence of corrupted simulation data and variations in simulation data from multiple sources.

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Thispaperpresents an empirical evaluation of two memory-efficient directory methods for malntalnlng coherent caches in large shared memory multiprocessors. Both directory methods are modifications of a scheme proposed by Censier and Feautrier [5] that does not rely on a specific interconnection network and can be readily distributed across interleaved main memory. The schemes considered here overcome the large amount of memory required for tags in the original scheme in two different ways. In the first scheme each main memory block is sectored into sub-blocks for which the large tag overhead is shared. In the second scheme a limited number of large tags are stored in an associative cache and shared among a much larger number of main memory blocks. Simulations show that in terms of access time and network traffic both directory methods provide significant performance improvements over a memory system in which shared-wrlteable data is not cached. The large block sizes required for the sectored scheme, however, promotes sufficient false sharing that its performance is markedly worse than using a tag cache.

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