Comprehensive performance re-assessment of TFETs with a novel design by gate and source engineering from device/circuit perspective

Huang, Qianqian; Huang, Ru; Wu, Chunlei; Zhu, Hao; Chen, Cheng; Wang, Jiaxin; Guo, Lingyi; Wang, Runsheng; Ye, Le; Wang, Yangyuan

doi:10.1109/iedm.2014.7047044

Cited by 50 publications

(17 citation statements)

References 2 publications

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“…也有很多研究者通过采用多栅结构、垂直隧穿结、杂质分凝、重掺杂插入层等方法试图提高隧穿几率. 北京大学的研究小组从工作原理角度出发, 提出了肖特基 (Schottky Barrier) 隧穿动态混合控制新机理, 研制出了一种新型 T 型栅肖特基隧穿晶体管 (TSB-TFET) [24] 和优化的梳状栅杂质分凝隧穿晶体管 (MFSB-TFET) [25] , 二者具有相同的版图面积, 能同时解决隧穿晶体管开态电流、亚阈除了隧穿晶体管之外, Purdue University 提出利用铁电绝缘介质的负电容现象实现了栅电压对表面势的放大 [19] , 这样等效地增大了栅电压的控制作用, 提高了亚阈值区的陡峭度. 但是这类器件只有在总体电容为正的情况下才能使铁电介质处于稳定负电容状态, 这对铁电介质材料的选择和厚度设计提出了非常苛刻的窗口, 制约这类器件的应用.…”

Section: 超陡峭开关器件unclassified

Micro/Nano-scale integrated circuits and new emerging hybrid integration techniques

Zeng¹,

Li²,

Chen³

et al. 2016

Sci. Sin.-Inf.

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曾晓洋等: 微纳集成电路和新型混合集成技术能力 [3]. 即使采取了诸多改进手段 UTBSOI 器件在推进到 10 nm 及以下节点时, 硅膜的厚度仍要求小于 5 nm, 这对于大规模制造而言存在极高的挑战. 不同于 UTBSOI 技术, FinFET 技术通过光刻和刻蚀工艺形成竖直的鱼鳍状超薄体沟道区 (fin), 栅电极跨越在沟道区上, 形成 "几" 字形的结构同时从顶端和侧面对沟道电荷进行控制 [2]. 这种结构使得 FinFET 器件的等比例缩小能力更强, 能够大幅放宽对沟道厚度 (fin 的宽度) 的要求, 而且版图面积效率高, 在相同集成密度下获得的驱动电流更大. FinFET 器件也存在与 UTBSOI 类似的共性问题, 比如寄生电阻、硅膜厚度涨落、迁移率退化、多阈值控制等. 不过, 近年来的大规模生产实践表明这些问题基本能够得到缓解. 相比较 UTBSOI, 体硅 FinFET 面临的一个较为特殊的问题是体区穿通的问题, 需要采用防穿通掺杂或者体区隔离等措施, 例如 BOI FinFET (body-on-insulator FinFET) 结构 [4]. 当 FinFET 器件进一步缩小时, 将会进化成围栅纳米线这一极限结构. 围栅纳米线器件具有最强的短沟道效应抑制能力. 围栅纳米线器件除了面临超薄体引起的共性问题之外, 还面临着更为严峻的制造工艺挑战, 即形成可控的纳米线结构. 为此, 三星电子提出利用 SiGe 外延和选择性腐蚀的方法制造悬空纳米线 [5] , IBM 提出在 SOI 衬底上对埋氧层进行选择性腐蚀和氢气退火形成边缘光滑的纳米线 [6] , 而北京大学提出了对硅 Fin 进行自限制氧化结合底部腐蚀形成悬空纳米线的方法 [7]. 从目前技术发展的趋势来看, FinFET 在 14 nm 以下节点是主流的器件结构, 并可能在 5 nm 及以下节点进化成为围栅纳米线器件形态, 而 UTBSOI 作为一种补充, 在一些特殊领域存在一定的应用.

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Section: 超陡峭开关器件unclassified

Micro/Nano-scale integrated circuits and new emerging hybrid integration techniques

Zeng¹,

Li²,

Chen³

et al. 2016

Sci. Sin.-Inf.

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“…Unfortunately, in conventional Si TFETs, as the gate-source voltage increases, BTBT rapidly approaches saturation, which causes SS AVG to increase dramatically. Hence, unlike conventional MOSFETs where SS AVG is approximately equal to SS MIN , the value of SS AVG in conventional Si TFETs is always considerably larger than SS MIN [19,20]. However, SS AVG dramatically increases as V gs increases, resulting in SS AVG and SS MIN differing considerably and SS AVG becoming unsteady.…”

Section: Introductionmentioning

confidence: 97%

A Novel Germanium-Around-Source Gate-All-Around Tunnelling Field-Effect Transistor for Low-Power Applications

et al. 2020

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This paper presents a germanium-around-source gate-all-around tunnelling field-effect transistor (GAS GAA TFET). The electrical characteristics of the device were studied and compared with those of silicon gate-all-around and germanium-based-source gate-all-around tunnel field-effect transistors. Furthermore, the electrical characteristics were optimised using Synopsys Sentaurus technology computer-aided design (TCAD). The GAS GAA TFET contains a combination of around-source germanium and silicon, which have different bandgaps. With an increase in the gate-source voltage, band-to-band tunnelling (BTBT) in silicon rapidly approached saturation since germanium has a higher BTBT probability than silicon. At this moment, germanium could still supply current increment, resulting in a steady and steep average subthreshold swing ( S S AVG ) and a higher ON-state current. The GAS GAA TFET was optimised through work function and drain overlapping engineering. The optimised GAS GAA TFET exhibited a high ON-state current ( I ON ) (11.9 μ A), a low OFF-state current ( I OFF ) ( 2.85 × 10 − 9 μ A), and a low and steady S S AVG (57.29 mV/decade), with the OFF-state current increasing by 10 7 times. The GAS GAA TFET has high potential for use in low-power applications.

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“…Considering the mentioned advantages of TFETs individual behavior, recent studies haves shown how basic circuits may be improved as well [20][21][22]. Digital configurations such as inverters and multiplexers have been analyzed, with a vast majority of studies based on simulations [23,24], but also a few with experimental data [25,26].…”

Section: Introductionmentioning

confidence: 99%

Analysis of current mirror circuits designed with line tunnel FET devices at different temperatures

Martino

Agopian

et al. 2017

Semicond. Sci. Technol.

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The goal of this work is to study the performance of current mirror circuits designed with line tunnel field effect transistor (TFET) devices and compare the suitability of this technology with alternatives such as point TFETs and FinFETs. Experimental results have been obtained at room and high temperatures and the analyses focused on parameters such as the magnitude of the onstate current and the sensitivity of the current transfer ratio to channel dimensions mismatch and to the temperature. Line TFETs exhibited higher on-state current than point TFETs, in spite of a higher susceptibility to the channel length. When band-to-band tunneling prevails for both input and output transistors, the current transfer ratio with line TFETs presented a nearly linear dependence on the temperature due to bandgap narrowing. This way, a general equation of the current transfer ratio for circuits designed with the three highlighted technologies is proposed. Globally, it was observed that, unless a very low sensitivity to channel length mismatch is required, line TFET devices are a very suitable alternative for current mirror circuits, since this technology provides much higher on-state currents than point TFETs, and at the same time it is much less sensitive to temperature variations than FinFET transistors.

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Comprehensive performance re-assessment of TFETs with a novel design by gate and source engineering from device/circuit perspective

Cited by 50 publications

References 2 publications

Micro/Nano-scale integrated circuits and new emerging hybrid integration techniques

Micro/Nano-scale integrated circuits and new emerging hybrid integration techniques

A Novel Germanium-Around-Source Gate-All-Around Tunnelling Field-Effect Transistor for Low-Power Applications

Analysis of current mirror circuits designed with line tunnel FET devices at different temperatures

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