Compressed code execution on DSP architectures

Centoducatte, Paulo Cesar; Araújo, Guido; Pannain, Ricardo

doi:10.1109/isss.1999.814261

Cited by 7 publications

(6 citation statements)

References 10 publications

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“…A significant portion of their work deals with the handling of the defragmentation of this procedure-cache. [Araújo et al 1998] [Centoducatte et al 1999] [Araújo et al 2000a[Araújo et al , 2000b Araújo, Centoducatte et al elaborated variants of their code compression techniques, whose basic characteristic is that the decompression is performed by a special hardware logic located in front of the CPU's instruction fetch unit. The decompression is done in real-time during program execution (i.e., the original instructions are generated during instruction fetch).…”

Section: Software-managedmentioning

confidence: 99%

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Survey of code-size reduction methods

et al. 2003

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Program code compression is an emerging research activity that is having an impact in several production areas such as networking and embedded systems. This is because the reduced-sized code can have a positive impact on network traffic and embedded system costs such as memory requirements and power consumption. Although code-size reduction is a relatively new research area, numerous publications already exist on it. The methods published usually have different motivations and a variety of application contexts. They may use different principles and their publications often use diverse notations. To our knowledge, there are no publications that present a good overview of this broad range of methods and give a useful assessment. This article surveys twelve methods and several related works appearing in some 50 papers published up to now. We provide extensive assessment criteria for evaluating the methods and offer a basis for comparison. We conclude that it is fairly hard to make any fair comparisons of the methods or draw conclusions about their applicability.

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Section: Software-managedmentioning

confidence: 99%

“…In the article [Centoducatte et al 1999], the authors adapted their previous method to DSP architectures (they applied it to a common DSP processor). The major difference with this method is that the expression trees are not decomposed, but they are encoded as a whole.…”

Section: Brief Classificationmentioning

confidence: 99%

Survey of code-size reduction methods

et al. 2003

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“…This implies that the decompression engine should be able to keep track of codeword boundaries inside the current memory word and to put together pieces of a split codeword during two consecutive memory fetches. In [9], we propose a variation of TBC for the TMS320C25 DSP.…”

Section: Tree-based Compressionmentioning

confidence: 99%

Expression-tree-based algorithms for code compression on embedded RISC architectures

Araújo

Centoducatte

Azevedo

et al. 2000

IEEE Trans. VLSI Syst.

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Reducing program size has become an important goal in the design of modern embedded systems targeted to mass production. This problem has driven efforts aimed at designing processors with shorter instruction formats (e.g., ARM Thumb and MIPS16) or able to execute compressed code (e.g., IBM PowerPC 405). This paper proposes three code compression algorithms for embedded RISC architectures. In all algorithms, the encoded symbols are extracted from program expression trees. The algorithms differ on the granularity of the encoded symbol, which are selected from whole trees, parts of trees, or single instructions. Dictionary-based decompression engines are proposed for each compression algorithm. Experimental results, based on SPEC CINT95 programs running on the MIPS R4000 processor, reveal an average compression ratio of 53.6% (31.5%) if the area of the decompression engine is (not) considered.Index Terms-Code compression, RISC architecture.

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“…Code compression efficiency is widely defined [4,12,15,19] as the ratio between the compressed program size and the original program size. That is, the smaller the compression ratio, the better the compression.…”

Section: Introductionmentioning

confidence: 99%

A hamming distance based VLIW/EPIC code compression technique

Ros

Sutton

2004

Proceedings of the 2004 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems

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This paper presents and reports on a VLIW code compression technique based on vector Hamming distances [19]. It investigates the appropriate selection of dictionary vectors such that all program vectors are at most a specified maximum Hamming distance from a dictionary vector. Bit toggling information is used to restore the original vector. A dictionary vector selection method which considered both vector frequency as well as maximum coverage achieved better results than just considering vector frequency or vector coverage independently. This method was found to outperform standard dictionary compression on TI TMS320C6x program code by an average of 8%, giving compression ratios of 72.1% to 80.3% when applied to the smallest compiler builds. The most favorable results were achieved with a Hamming distance upper limit of 3. An investigation into parallel compression showed that dividing the program into 32-bit parallel streams returned an average compression ratio of 79.4% for files larger than 200kb. This approach enables parallel decompression of instruction streams within a VLIW instruction word. Suggestions for further work include compiler/compression integration, more sophisticated dictionary selection methods and better codeword allocation. It investigates the appropriate selection of dictionary vectors such that all program vectors are at most a specified maximum Hamming distance from a dictionary vector. Bit toggling information is used to restore the original vector.A dictionary vector selection method which considered both vector frequency as well as maximum coverage achieved better results than just considering vector frequency or vector coverage independently. This method was found to outperform standard dictionary compression on TI TMS320C6x program code by an average of 8%, giving compression ratios of 72.1% to 80.3% when applied to the smallest compiler builds. The most favorable results were achieved with a Hamming distance upper limit of 3.An investigation into parallel compression showed that dividing the program into 32-bit parallel streams returned an average compression ratio of 79.4% for files larger than 200kb. This approach enables parallel decompression of instruction streams within a VLIW instruction word. Suggestions for further work include compiler/compression integration, more sophisticated dictionary selection methods and better codeword allocation.

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Compressed code execution on DSP architectures

Cited by 7 publications

References 10 publications

Survey of code-size reduction methods

Survey of code-size reduction methods

Expression-tree-based algorithms for code compression on embedded RISC architectures

A hamming distance based VLIW/EPIC code compression technique

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