Compressed tag architecture for low-power embedded cache systems

A survey of architectural techniques for improving cache power efficiency

“…This enables the processor to sustain a higher instruction rate, which improves both performance and energy efficiency. [38], [55], [63]- [65], memory storage for prediction of cache access result [11], [14], [15], [49], [66] for pre-determination of cache access result [18], [28], [50], [67]- [69] Reducing number using software [17], of ways consulted compiler [40], [57] , in each access hardware [12], [28], [47], [49], [50], [67], [69], [70] Reducing switching Sequential cache-way access [14], [37], [49], [54], activity multi-step tag-bit matching [71], reducing active tag bits or those actually compared [22], [34], [72]- [74] accessing frequent (hot) data with lower energy [21], [46] ESTs for multicores [57], [66], [75] or multiprocessors Ghosh et al [67] propose a technique named 'Way Guard' to save dynamic energy in caches. This technique uses a segmented counting Bloom filter [77] with each cache way.…”

“…Kwak and Jeon [72] propose a technique to reduce the power consumed in tag-accesses. Their technique works on the observation that since program applications typically exhibit high memory access locality, most of the tag bits of successive memory addresses are expected to be same, except for a few differences in the LSB-side bits.…”

“…If a cache hit/miss decision has already been taken, further tasks can be avoided for saving dynamic energy. For example, a few techniques access cache ways sequentially [14], [37], [49], [54]; some other techniques perform matching of tag-bits in multi-step manner [71], while some techniques reduce the number of tag bits which are active or are required for comparison [22], [34], [72]- [74]. Techniques have also been proposed which reduce the data transferred in each cache access (e.g., [76]).…”

Hybrid approach based on partial tag comparison technique and search methods to improve cache performance

“…A cache architecture presented in [18] provides system performance that is comparable against regular cache systems with up to 27.8% energy saving. The proposed cache architecture moves most tag bits into the locality buffer, and tag compression to produce a new tag matching that use partial tag matching instead of full tag matching.…”