Computation and refinement of statistical bounds on circuit delay

Agarwal, Aseem; Blaauw, David; Zolotov, Vladimir; Vrudhula, S.

doi:10.1109/dac.2003.1219022

“…We will be mainly concerned about the latter case, since the performance/energy tradeoff is an outstanding issue in system design. Some recent work on statistical timing analysis [1] focuses on better tolerating process variations. Nonetheless, clock frequencies are almost always set on the basis of the longest propagation delay in the worst-case environmental situation (e.g., temperature, voltage, and local charge).…”

Section: A Self-calibrating Designmentioning

confidence: 99%

A robust self-calibrating transmission scheme for on-chip networks

Worm

¹

,

Ienne

²

,

Thiran

³

et al. 2005

IEEE Trans. VLSI Syst.

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Abstract-Systems-on-Chip (SoC) design involves several challenges, stemming from the extreme miniaturization of the physical features and from the large number of devices and wires on a chip. Since most SoCs are used within embedded systems, specific concerns are increasingly related to correct, reliable, and robust operation. We believe that in the future most SoCs will be assembled by using large-scale macro-cells and interconnected by means of on-chip networks. In this paper, we examine some physical properties of on-chip interconnect busses, with the goal of achieving fast, reliable, and low-energy communication. These objectives are reached by dynamically scaling down the voltage swing, while ensuring data integrity-in spite of the decreased signal to noise ratio-by means of encoding and retransmission schemes. In particular, we describe a closed-loop voltage swing controller that samples the error retransmission rate to determine the operational voltage swing. We present a control policy which achieves our goals with minimal complexity; such simplicity is demonstrated by implementing the policy in a synthesizable controller. Such a controller is an embodiment of a self-calibrating circuit that compensates for significant manufacturing parameter deviations and environmental variations. Experimental results show that energy savings amount up to 42%, while at the same time meeting performance requirements.Index Terms-Electrical parameter variations, interconnect for networks-on-chip, low-power systems-on-chip (SoC), self-calibrating designs, VLSI design methodology.

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“…Furthermore, these variations are increasing with each new generation of technology. Statistical Static Timing Analysis (SSTA) has been proposed to perform full-chip analysis of timing under such types of uncertainty, and has been the subject of intense research recently [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18]. The result of SSTA is the prediction of parametric yield at a given target performance for a design.…”

Section: Introductionmentioning

confidence: 99%

An accurate sparse-matrix based framework for statistical static timing analysis

Ramalingam

¹

,

Singh

²

,

Nassif

³

et al. 2012

Integration

3

0

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Statistical Static Timing Analysis has received wide attention recently and emerged as a viable technique for manufacturability analysis. To be useful, however, it is important that the error introduced in SSTA be significantly smaller than the manufacturing variations being modeled. Achieving such accuracy requires careful attention to the delay models and to the algorithms applied. In this paper, we propose a new sparse-matrix based framework for accurate path-based SSTA, motivated by the observation that the number of timing paths in practice is sub-quadratic based on a study of industrial circuits and the ISCAS89 benchmarks. Our sparse-matrix based formulation has the following advantages: (a) It places no restrictions on process parameter distributions; (b) It embeds accurate polynomial-based delay model which takes into account slope propagation naturally; (c) It takes advantage of the matrix sparsity and high performance linear algebra for efficient implementation. Our experimental results are very promising.

show abstract

“…Furthermore, these variations are increasing with each new generation of technology. Statistical Static Timing Analysis (SSTA) has been proposed to perform full-chip analysis of timing under such types of uncertainty, and has been the subject of intense research recently [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18]. The result of SSTA is the prediction of parametric yield at a given target performance for a design.…”

Section: Introductionmentioning

confidence: 99%

An Accurate Sparse Matrix Based Framework for Statistical Static Timing Analysis

Ramalingam

¹

,

Nam

²

,

Singh

³

et al. 2006

2006 IEEE/ACM International Conference on Computer Aided Design

View full text Add to dashboard Cite

Statistical Static Timing Analysis has received wide attention recently and emerged as a viable technique for manufacturability analysis. To be useful, however, it is important that the error introduced in SSTA be significantly smaller than the manufacturing variations being modeled. Achieving such accuracy requires careful attention to the delay models and to the algorithms applied. In this paper, we propose a new sparse-matrix based framework for accurate path-based SSTA, motivated by the observation that the number of timing paths in practice is sub-quadratic based on a study of industrial circuits and the ISCAS89 benchmarks. Our sparse-matrix based formulation has the following advantages: (a) It places no restrictions on process parameter distributions; (b) It embeds accurate polynomial-based delay model which takes into account slope propagation naturally; (c) It takes advantage of the matrix sparsity and high performance linear algebra for efficient implementation. Our experimental results are very promising.

show abstract

Computation and refinement of statistical bounds on circuit delay

Cited by 43 publications

References 7 publications

A robust self-calibrating transmission scheme for on-chip networks

A robust self-calibrating transmission scheme for on-chip networks

An accurate sparse-matrix based framework for statistical static timing analysis

An Accurate Sparse Matrix Based Framework for Statistical Static Timing Analysis

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