2017
DOI: 10.1117/12.2259750
|View full text |Cite
|
Sign up to set email alerts
|

Computational scanner wafer mark alignment

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
3
1
1

Citation Types

0
9
0

Year Published

2018
2018
2024
2024

Publication Types

Select...
3
3

Relationship

0
6

Authors

Journals

citations
Cited by 7 publications
(9 citation statements)
references
References 0 publications
0
9
0
Order By: Relevance
“…The input parameters of the simulation system include the mark type, segmentation method, device pattern information, design rule and full stack information (such as material thickness, n and k). Through a series of simulation calculations, the corresponding KPIs will be the output as the evaluation of the alignment position deviation and reproducibility to help reduce the overlay contribution from alignment marks 41,44 .…”
Section: Development Of Alignment Marks and Efficient Methods For Mar...mentioning
confidence: 99%
See 1 more Smart Citation
“…The input parameters of the simulation system include the mark type, segmentation method, device pattern information, design rule and full stack information (such as material thickness, n and k). Through a series of simulation calculations, the corresponding KPIs will be the output as the evaluation of the alignment position deviation and reproducibility to help reduce the overlay contribution from alignment marks 41,44 .…”
Section: Development Of Alignment Marks and Efficient Methods For Mar...mentioning
confidence: 99%
“…For instance, asymmetry may be induced, the duty cycle may change and the phase depth of the alignment mark may be altered 45 . Among them the asymmetry causes a phase change of the diffraction beam, as shown in figure 10, and such phase change will induce the alignment position deviation (APD) and overlay error 44,46 .…”
Section: Optimal Color Weighting Algorithmmentioning
confidence: 99%
“…The overlay error beyond the limitation may cause gross deviation of the IC components and devices, and lead to short circuits, open circuits and other problems [3][4][5]. According to the International Technology Roadmap for Semiconductors (ITRS) and other institutes, for process nodes of 10 nm and 7 nm, the overlay accuracy is required to be below 3 nm and 2 nm [6][7][8][9][10].…”
Section: Introductionmentioning
confidence: 99%
“…Currently, several methods are employed to correct alignment position error, including the process verification method, multi-diffraction order-weighted method and multi-channel-weighted method. In the process verification method, the overlay error of the two layers is precisely measured using scanning electron microscopy (SEM) after lithography, and the alignment position error will be corrected in the subsequent process based on the measured overlay error [6,17,22]. However, since the mark asymmetries differ between wafers and exposure fields, even for the same batch and process, this method can not correct the alignment error stably.…”
Section: Introductionmentioning
confidence: 99%
See 1 more Smart Citation