Compute-in-eDRAM with Backend Integrated Indium Gallium Zinc Oxide Transistors

Abstract

With rapid growth in data intensive applications, there is an ever-increasing need for energy efficient machine learning/AI hardware accelerators. The performance and the energy efficiency of such accelerators are primarily limited due of massive amount of data movement between processing engines and the off-chip memory. This memory wall bottleneck can be mitigated by performing accelerator specific computations in the memory (CIM) array embedded with the rest of the logic blocks. Multiple embedded memory technologies are being explored to advance CIM designs. Among these, embedded Dynamic Random Access Memory (eDRAM) using backend of the line (BEOL) integrated C-Axis Aligned Crystalline (CAAC) Indium Gallium Zinc Oxide (IGZO) transistors is a promising candidate. IGZO transistor having extremely low leakage when used as an access transistor of the eDRAM bitcell can enable multi-level cell (MLC) eDRAM functionality. Moreover, higher bandwidth can be achieved by 3D stacking multiple layers of BEOL integrated IGZO devices in a monolithic manner improving the CIM performance. In this paper, we analyze various IGZO based eDRAM bitcell topologies and present an IGZO eDRAM CIM architecture. It supports 8-bit inputs/activations and 8-bit signed weights. 2-bit Flash Analog to Digital converter (ADC) is used for MLC weight bit read sensing. A representative neural network model using IGZO eDRAM and peripheral 8-b A/D converters based CIM design achieves 80% Top-1 inference accuracy for the CIFAR-10 dataset, which is within 3% of ideal software accuracy.

A Review on Non-Volatile and Volatile Emerging Memory Technologies

“…Therefore, these offer the advantage of improved performance at the cost of lesser retention time. To further improve the retention time and reduce the leakage of eDRAMs, few novel materials based devices like Indium Gallium Zinc Oxide eDRAMs have been proposed, which have extreme low leakage with moderate ON currents have been proposed [18,19].…”

An N-Type Pseudo-Static eDRAM Macro with Reduced Access Time for High-Speed Processing-in-Memory in Intelligent Sensor Hub Applications

“…As an alternative, several studies have suggested PIM approaches based on embedded dynamic RAM (eDRAM) [16][17][18][19]. Compatible with general logic processes, eDRAM provides higher integration and smaller area compared to those of SRAM [20].…”

Pseudo-Static Gain Cell of Embedded DRAM for Processing-in-Memory in Intelligent IoT Sensor Nodes

“…In addition, eDRAM can be implemented in any CMOS process without the use of an additional layer. To overcome these limitations, PIMs with embedded dynamic random-acc memory (eDRAM) have been proposed [11][12][13]. Logic-compatible eDRAMs [14][15][16][17] c offer a higher bit density and smaller area than those of the SRAMs.…”

“…Therefore, process-independent retention time extension is required without the use of an additional capacitor in the eDRAM gain cell. To overcome these limitations, PIMs with embedded d memory (eDRAM) have been proposed [11][12][13]. Logic-compatib offer a higher bit density and smaller area than those of the SRAM based PIM can realize more area-efficient implementation than t PIM.…”