Computer Evaluation of a Method for Combinational-Circuit Synthesis in FPGAs

Shalagin, S. V.

doi:10.1023/b:rumi.0000011100.81232.da

Cited by 5 publications

(1 citation statement)

References 2 publications

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“…According to [7,8], a FPGA-based combinational circuit close to the optimal implementation requires involving at most 0.5 of the resources of each type, i.e., D-triggers, LUTs, Slices, and input/output units.…”

Section: Discussionmentioning

confidence: 99%

Distributed image processing based on the same IP-cores in FPGA-architecture

Zakharov

Shalagin²,

Eminov

2019

Proceedings of the v International Conference Information Technology and Nanotechnology 2019

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The problem of processing images, i. e., two-dimensional data arrays, was solved through implementing two-dimensional fast Fourier transform (FFT) when using single-type hardware modules – IP-cores in the Virtex-6 FPGA architecture. We have shown the possibility of the parallel implementation of each stage in the two-dimensional FFT, based on four “butterfly”-type transforms (BTr) over four elements of the data array being processed. Estimations were obtained regarding time- and hardware complexity of the IPcore implementing BTrs and used in implementing the one-dimensional FFT. The results obtained can be used in estimating hardware and time consumption when performing a twodimensional FFT over an array of the pre-defined dimensionality in using existing and forthcoming distributed programmable-architecture systems.

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Section: Discussionmentioning

confidence: 99%

Distributed image processing based on the same IP-cores in FPGA-architecture

Zakharov

Shalagin²,

Eminov

2019

Proceedings of the v International Conference Information Technology and Nanotechnology 2019

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Using the same type of IP-cores in the Virtex-6 family FPGA-architecture for distributed image processing

Zakharov

Shalagin

Eminov³

2020

J. Phys.: Conf. Ser.

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Distributed image processing in real time is a relevant task. An effective solution to this problem at the hardware level is possible on the basis of creating prototypes of devices on FPGA. In this regard, the paper solves the problem of distributed computation of two-dimensional fast Fourier transform (TDFFT) based on the same type of IP-cores implemented in the architecture of the Virtex-6 family_FPGA-architecture. The possibility of distributed implementation of each of the stages of the TDFFT, performed using four transformations of the “butterfly” type_(TrB) over four elements of the processed data array, is shown. When using a specialized CAD-system, estimates of the time and hardware complexity of the IP-core implementing TrB are_obtained. The estimated operating frequency of this_IP-core is approximately 108 MHz. Hardware complexity estimates by the number of configurable elements involved in the Virtex-6 family_FPGA-architecture are determined. TrB must be performed over an_array of N 2 elements a · N 2/4 once, where a = log2 N is the number of TDFFT stages, and N = 2 k . The ability to parallelize the specified operations at each of a stages by using_IP-cores that implement four TrB is shown. The results can be used to estimate hardware and time costs for distributed TDFFT execution over a square data array N × N - dimension.

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Implementing the Markov Probability Functions Based on a Set of Polynomials over Galois Field

Shalagin

Zakharov

2021

2021 International Conference on Information Technology and Nanotechnology (ITNT)

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Computer Evaluation of a Method for Combinational-Circuit Synthesis in FPGAs

Cited by 5 publications

References 2 publications

Distributed image processing based on the same IP-cores in FPGA-architecture

Distributed image processing based on the same IP-cores in FPGA-architecture

Using the same type of IP-cores in the Virtex-6 family FPGA-architecture for distributed image processing

Implementing the Markov Probability Functions Based on a Set of Polynomials over Galois Field

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