Computing Accurate AVFs using ACE Analysis on Performance Models: A Rebuttal

Biswas, Arijit; Racunas, Paul; Emer, Joel; Mukherjee, S.

doi:10.1109/l-ca.2007.19

Cited by 37 publications

(17 citation statements)

References 4 publications

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“…Wang et al show that lack of model detail in ACE Analysis can lead to overly conservative AVF estimates [10]. This was shown to not be a fundamental limitation of the technique, however, and the authors themselves conclude that AVF Analysis is an indispensable tool for early-design reliability analysis [11]. Li et al show that FIT rates calculated using average AVF values may be inaccurate since AVF values are often not independent [12].…”

Section: Architectural Vulnerability Factormentioning

confidence: 99%

Eliminating microarchitectural dependency from Architectural Vulnerability

Sridharan

Kaeli

2009

2009 IEEE 15th International Symposium on High Performance Computer Architecture

137

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The Architectural Vulnerability Factor (AVF) of a hardware structure is the probability that a fault in the structure will affect the output of a program. AVF captures both microarchitectural and architectural fault masking effects; therefore, AVF measurements cannot generate insight into the vulnerability of software independent of hardware. To evaluate the behavior of software in the presence of hardware faults, we must isolate the software-dependent (architecture-level masking) portion of AVF from the hardware-dependent (microarchitecture-level masking) portion, providing a quantitative basis to make reliability decisions about software independent of hardware.In this work, we demonstrate that the new Program Vulnerability Factor (PVF) metric provides such a basis: PVF captures the architecture-level fault masking inherent in a program, allowing software designers to make quantitative statements about a program's tolerance to soft errors. PVF can also explain the AVF behavior of a program when executed on hardware; PVF captures the workload-driven changes in AVF for all structures. Finally, we demonstrate two practical uses for PVF: choosing algorithms and compiler optimizations to reduce a program's failure rate.

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Section: Architectural Vulnerability Factormentioning

confidence: 99%

Eliminating microarchitectural dependency from Architectural Vulnerability

Sridharan

Kaeli

2009

2009 IEEE 15th International Symposium on High Performance Computer Architecture

137

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“…Their results corroborated that ACE analysis overestimates microprocessor vulnerability, mostly due to less detailed structures available in the performance model employed in [15].Furthermore, recent radiation studies with actual proton and neutron irradiation tests showed that SFI measurements closely match in-field exposure [18]. While [19] shows that ACE inaccuracy can be reduced by adding extra detail to the employed model, accurate AVF analysis heavily relies on the existence of a detailed RTL model.…”

Section: Related Workmentioning

confidence: 69%

Investigating the limits of AVF analysis in the presence of multiple bit errors

Maniatakos

Michael

Makris

2013

2013 IEEE 19th International on-Line Testing Symposium (IOLTS)

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We investigate the complexity and utility of performing Multiple Bit Upset (MBU) vulnerability analysis in modern microprocessors. While the Single Bit Flip (SBF) model constitutes the prevailing mechanism for capturing the effect of Single Event Upsets (SEUs) due to alpha particle or neutron strikes in semiconductors, recent radiation studies in 90nm and 65nm technology nodes demonstrate that up to 55% of such strikes result in Multiple Bit Upsets (MBUs). Consequently, the accuracy of popular vulnerability analysis methods, such as the Architecural Vulnerability Factor (AVF) and Failures In Time (FIT) rate estimates based on the SBF assumption comes into question, especially in modern microprocessors which contain a significant amount of memory elements. Towards alleviating this concern, we present an extensive infrastructure which enables MBU vulnerability analysis in modern microprocessors. Using this infrastructure and a modern microprocessor model, we perform a large scale MBU vulnerability analysis study and we report two key findings: (i) the SBF fault model overestimates vulnerability by up to 71%, as compared to a more realistic modeling and distribution of faults in the 90nm and 65nm processes, and (ii) the rank-ordered lists of critical bits, as computed through the SBF and MBU models, respectively, are very similar, as indicated by the average rank difference of a bit which is less than 1.45%.

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“…Physical interleaving, on the other hand, assigns physically-adjacent bits to different data words, thus ensuring adjacent bits are protected by different [41]. This analysis was rebutted, and the effects pointed out by Wang were incorporated into an ACE analysis infrastructure [8]. Sridharan and Kaeli extended the notion of vulnerability to allow independent measurement of the vulnerability of programs and hardware [32] [33].…”

Section: Existing Multi-bit Remediation Techniquesmentioning

confidence: 99%

Calculating Architectural Vulnerability Factors for Spatial Multi-Bit Transient Faults

Wilkening

Sridharan

et al. 2014

2014 47th Annual IEEE/ACM International Symposium on Microarchitecture

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Abstract-Reliability is an important design constraint in modern microprocessors, and one of the fundamental reliability challenges is combating the effects of transient faults. This requires extensive analysis, including significant fault modeling to allow architects to make informed reliability tradeoffs. Recent data shows that multi-bit transient faults are becoming more common, increasing from 0.5% of SRAM faults in 180nm to 3.9% in 22nm, and are predicted to be even more prevalent in smaller technology nodes. Therefore, accurately modeling the effects of multi-bit transient faults is increasingly important to the microprocessor design process.Architecture vulnerability factor (AVF) analysis is a method to model the effects of single-bit transient faults. In this paper, we propose a method to calculate AVFs for spatial multi-bit transient faults (MB-AVFs) and provide insights that can help reduce the impact of these faults. First, we describe a novel multi-bit AVF analysis approach for detected, uncorrected errors (DUEs) and show how to measure DUE MB-AVFs in a performance simulator. We then extend our approach to measure SDC MB-AVFs. We find that MB-AVFs are not derivable from single-bit AVFs. We also find that larger fault modes have higher MB-AVFs. Finally, we present a case study on using MB-AVF analysis to optimize processor design, yielding SDC reductions of 86% in a GPU vector register file.

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Computing Accurate AVFs using ACE Analysis on Performance Models: A Rebuttal

Cited by 37 publications

References 4 publications

Eliminating microarchitectural dependency from Architectural Vulnerability

Eliminating microarchitectural dependency from Architectural Vulnerability

Investigating the limits of AVF analysis in the presence of multiple bit errors

Calculating Architectural Vulnerability Factors for Spatial Multi-Bit Transient Faults

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