Computing with ferroelectric FETs: Devices, models, systems, and applications

Aziz, Ahmedullah; Breyer, Evelyn T.; Chen, An; Chen, Xiaoming; Datta, Suman; Gupta, Sumeet Kumar; Hoffmann, Michael; Hu, Xiaobo Sharon; Ionescu, Adrian M.; Jerry, Matthew; Mikolajick, Thomas; Mulaosmanovic, Halid; Ni, Kai; Niemier, Michael; O’Connor, Ian; Saha, Atanu; Slesazeck, Stefan; Thirumala, Sandeep Krishna; Yin, Xunzhao

doi:10.23919/date.2018.8342213

Cited by 62 publications

(31 citation statements)

References 59 publications

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“…A model based on the time-dependent Landau Khalatnikov (LK) equations [12] has been used to describe the switching behavior of FeFETs [13]- [15]. However, actual FE switching dynamics are not easily modeled by the LK equation, which assumes a single-domain ferroelectric (FE) material with a single coercive field for the whole FE thin film.…”

Section: B Fefet Modelsmentioning

confidence: 99%

Design and Analysis of an Ultra-Dense, Low-Leakage, and Fast FeFET-Based Random Access Memory Array

Reis

Datta

Niemier

et al. 2019

IEEE J. Explor. Solid-State Comput. Devices Circuits

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High static power associated with static random access memory (SRAM) represents a bottleneck in increasing the amount of on-chip memory. Novel, emerging nonvolatile memories such as spintransfer torque magnetic random access memory (STT-RAM), resistive random access memory (RRAM), and ferroelectric field effect transistor-based random access memory (FeFET-RAM) are alternatives for replacing hardware kernels such as SRAM-based last level caches (LLC) due to their fast access times and lower leakage. In this paper, we study an ultra-dense FeFET-RAM based on 1-FeFET memory cells, and address potential disturbance issues at the array level. Disturbances are studied experimentally and via simulation. Experimental measurements are well correlated with modeling results suggesting that we have a good understanding of how disturbance issues will manifest themselves. That said, previous WRITE schemes for 1-FeFET arrays may: 1) exacerbate disturbances and 2) significantly degrade figures of merit (FoM) such as WRITE power. To address these issues, we propose the use of columnwise body connections to simultaneously overcome disturbances and reduce leakage currents during WRITES. We present detailed studies on how 1-FeFET memory cells and arrays (with columnwise body bias) fare when compared to traditional SRAM approaches and other emerging technologies. Notably, we benchmark the 1-FeFET memory against 1T + 1FeFET and 2T + 1FeFET designs proposed in early works, as well as SRAM, STT-RAM, and RRAM. Our evaluation of a 64×64 FeFET-RAM array shows that the area, READ delay, and static power are reduced by ∼5.3×, ∼1.5×, and ∼74×, respectively, when compared to an SRAM equivalent. Also, the 1-FeFET memory cell design shows ∼50× improvements in terms of WRITE energy with respect to STT-RAM and RRAM counterparts. INDEX TERMS Emerging technologies, FeFETs, memory. I. INTRODUCTION In state-of-the-art processors, cache structures are typically comprised of complementary metal-oxide-semiconductor (CMOS) static random access memory (SRAM) cells. While transistor scaling has helped to reduce memory cost and improve cache capacity, low density and high leakage power associated with MOSFET SRAMs make it challenging to satisfy the growing memory demands from data intensive programs via 2-D CMOS-based SRAMs. The aforementioned challenges with SRAM have led to the search for alternative on-chip memory structures. Nonvolatile memories based on emerging technologies such as spin-transfer torque magnetic random access memory (STT-RAM), resistive random access memory (RRAM), and phase-change memory (PCM) have

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Section: B Fefet Modelsmentioning

confidence: 99%

Design and Analysis of an Ultra-Dense, Low-Leakage, and Fast FeFET-Based Random Access Memory Array

Reis

Datta

Niemier

et al. 2019

IEEE J. Explor. Solid-State Comput. Devices Circuits

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“…FeFET is a semiconductor device that has a similar structure as the MOSFET or FinFET, except that an additional layer of ferroelectric (FE) material is integrated into the stack of gate terminal (Aziz et al, 2018). The spontaneous polarization of the FE layer is reversible under a certain electric field applied in the correct direction.…”

Section: Methodsmentioning

confidence: 99%

“…The polarization depends on the current electric field and its history, resulted in a hysteresis loop. For further details, interested readers are pointed to Aziz et al (2018). Such a feature of FE layer induces a FeFET to switch “on” at a high voltage and “off” at a low applied gate voltage.…”

Section: Methodsmentioning

confidence: 99%

A Swarm Optimization Solver Based on Ferroelectric Spiking Neural Networks

et al. 2019

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As computational models inspired by the biological neural system, spiking neural networks (SNN) continue to demonstrate great potential in the landscape of artificial intelligence, particularly in tasks such as recognition, inference, and learning. While SNN focuses on achieving high-level intelligence of individual creatures, Swarm Intelligence (SI) is another type of bio-inspired models that mimic the collective intelligence of biological swarms, i.e., bird flocks, fish school and ant colonies. SI algorithms provide efficient and practical solutions to many difficult optimization problems through multi-agent metaheuristic search. Bridging these two distinct subfields of artificial intelligence has the potential to harness collective behavior and learning ability of biological systems. In this work, we explore the feasibility of connecting these two models by implementing a generalized SI model on SNN. In the proposed computing paradigm, we use SNNs to represent agents in the swarm and encode problem solutions with the spike firing rate and with spike timing. The coupled neurons communicate and modulate each other's action potentials through event-driven spikes and synchronize their dynamics around the states of optimal solutions. We demonstrate that such an SI-SNN model is capable of efficiently solving optimization problems, such as parameter optimization of continuous functions and a ubiquitous combinatorial optimization problem, namely, the traveling salesman problem with near-optimal solutions. Furthermore, we demonstrate an efficient implementation of such neural dynamics on an emerging hardware platform, namely ferroelectric field-effect transistor (FeFET) based spiking neurons. Such an emerging in-silico neuron is composed of a compact 1T-1FeFET structure with both excitatory and inhibitory inputs. We show that the designed neuromorphic system can serve as an optimization solver with high-performance and high energy-efficiency.

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“…Besides utilizing FeFET as nonvolatile memory [12]- [14], there have been a few recent works exploring FeFET based logic (AND, OR, etc.) design [15], oscillator design [16], spiking neural network [17], and binary neural network acceleration (using four FeFET cells for XNOR logic) [18]. These works focus on device/crossbar modeling and lack of system/architecture level design.…”

Section: Fefet Backgroundmentioning

confidence: 99%

“…For computation, the weights are stored as transistor channel conductance (i.e., threshold voltage), and input vectors are used to drive WLs (i.e., transistor gate). We employ FeFET-based AND logic [15] to perform the 1-bit multiplication. One-bit of weight is encoded as high V th or low V th , representing either 0 or 1, respectively; similarly, 1 bit of input vector can be encoded as high or low WL voltage (V gs ).…”

Section: Fefet Crossbar Designmentioning

confidence: 99%

A Ferroelectric FET-Based Processing-in-Memory Architecture for DNN Acceleration

Long

Kim

Lee

et al. 2019

IEEE J. Explor. Solid-State Comput. Devices Circuits

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This paper presents a ferroelectric FET (FeFET)-based processing-in-memory (PIM) architecture to accelerate the inference of deep neural networks (DNNs). We propose a digital in-memory vector-matrix multiplication (VMM) engine design utilizing the FeFET crossbar to enable bit-parallel computation and eliminate analog-to-digital conversion in prior mixed-signal PIM designs. A dedicated hierarchical network-on-chip (H-NoC) is developed for input broadcasting and on-the-fly partial results processing, reducing the data transmission volume and latency. Simulations in 28-nm CMOS technology show 115× and 6.3× higher computing efficiency (GOPs/W) over desktop GPU (Nvidia GTX 1080Ti) and resistive random access memory (ReRAM)-based design, respectively. INDEX TERMS Deep neural network (DNN), ferroelectric FET (FeFET), processing-in-memory (PIM).

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Computing with ferroelectric FETs: Devices, models, systems, and applications

Cited by 62 publications

References 59 publications

Design and Analysis of an Ultra-Dense, Low-Leakage, and Fast FeFET-Based Random Access Memory Array

Design and Analysis of an Ultra-Dense, Low-Leakage, and Fast FeFET-Based Random Access Memory Array

A Swarm Optimization Solver Based on Ferroelectric Spiking Neural Networks

A Ferroelectric FET-Based Processing-in-Memory Architecture for DNN Acceleration

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