Concatenated non-binary LDPC and HD-FEC codes for 100Gb/s optical transport systems

Choi, Chang Soo; Lee, Hanho; Kaneda, Noriaki; Chen, Young-Kai

doi:10.1109/iscas.2012.6271611

Cited by 9 publications

(15 citation statements)

References 14 publications

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“…These symbols are used in the delta-to-normal domain conversion at the VN processor. Table I summarizes the minimum information to be exchanged to the VN processor in terms of bits, and also the numerical results for the (2304,2048) NB-LDPC code over GF(16), where H is constructed following the methods in [7] [11]. In this code, d c = 36, d v = 4 and the number of bits for the quantized messages are w = 5.…”

Section: Proposed Decoder Architecturementioning

confidence: 99%

“…Thus, we remove any redundant information and only keep the minimum set of values required to reconstruct all the messages at the VN processor. The proposed decoder architecture is implemented on a Virtex-7 FPGA for a (2304,2048) NB-LDPC code over GF(16) [7]. It needs 83% less memory resources in comparison with a conventional implementation of T-MM algorithm [6] without introducing any performance loss.…”

Section: Introductionmentioning

confidence: 99%

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A 630 Mbps non-binary LDPC decoder for FPGA

Lacruz

García-Herrero

Canet

et al. 2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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Abstract-A high-speed non-binary LDPC decoder based on Trellis Min-Max algorithm with layered schedule is presented. The proposed approach compresses the check-node output messages into a reduced set, decreasing the number of messages sent to the variable node. Additionally, the memory resources from the layered architecture are reduced. The proposed decoder was implemented for the (2304,2048) NB-LDPC code over GF(16) on a Virtex-7 FPGA and in a 90 nm CMOS process. Our implementation outperforms state-of-the-art NB-LDPC decoder implementations for both technologies, achieving a throughput of 630 and 965 Mbps, respectively.

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Section: Proposed Decoder Architecturementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A 630 Mbps non-binary LDPC decoder for FPGA

Lacruz

García-Herrero

Canet

et al. 2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…Additionally, they improve the burst error-correction capability and work in conjunction with high-order modulation schemes (16QAM, 64QAM, 256QAM) [7,8]. Nowadays, NB-LDPC codes have been considered strong candidates to be used in the 100Gbps optical transport system [9,10]. These systems require Soft-Decision (SD) decoding strategies that provide 10dB of Net Coding Gain (NCG) at a BER = 10 −15 , with a maximum overhead of 20% and code rate higher than 0.8.…”

Section: Prefacementioning

confidence: 99%

“…The proposed decoder architecture is implemented on a Virtex-7 FPGA for a (2304,2048) NB-LDPC code over GF (16) [10]. It needs 83% less memory resources in comparison with a conventional implementation of T-MM algorithm [42] without introducing any performance loss.…”

Section: Basis On Nb-ldpc Codes and T-mm Decoding Algorithmmentioning

confidence: 99%

“…These symbols are used in the delta-to-normal domain conversion at the VN processor. Table 5.1 summarizes the minimum information to be exchanged to the VN processor in terms of bits, and also the numerical results for the (2304,2048) NB-LDPC code over GF (16), where H is constructed following the methods in [10] [36]. In this code, d c = 36, d v = 4 and the number of bits for the quantized messages are w = 5.…”

Section: Check-node Architecturementioning

confidence: 99%

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VLSI algorithms and architectures for non-binary-LDPC decoding

Lacruz¹,

Jesús²

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This thesis studies the design of low-complexity soft-decision Non-Binary LowDensity Parity-Check (NB-LDPC) decoding algorithms and their corresponding hardware architectures suitable for decoding high-rate codes at high throughput (hundreds of Mbps and Gbps).In the first part of the thesis the main aspects concerning to the NB-LDPC codes are analyzed, including a study of the main bottlenecks of conventional softdecision decoding algorithms (Q-ary Sum of Products (QSPA), Extended MinSum (EMS), Min-Max and Trellis-Extended Min-Sum (T-EMS)) and their corresponding hardware architectures. Despite the limitations of T-EMS algorithm (high complexity in the Check Node (CN) processor, wiring congestion due to the high number of exchanged messages between processors and the inability to implement decoders over high-order Galois fields due to the high decoder complexity), it was selected as starting point for this thesis due to its capability to reach high-throughput.Taking into account the identified limitations of the T-EMS algorithm, the second part of the thesis includes six papers with the results of the research made in order to mitigate the T-EMS disadvantages, offering solutions that reduce the area, the latency and increase the throughput compared to previous proposals from literature without sacrificing coding gain. Specifically, five low-complexity decoding algorithms are proposed, which introduce simplifications in different parts of the decoding process. Besides, five complete decoder architectures are designed and implemented on a 90nm Complementary Metal-Oxide-Semiconductor (CMOS) technology. The results show an achievement in throughput higher than 1Gbps and an area less than 10 mm 2 . The increase in throughput is 120% and the reduction in area is 53% compared to previous implementations of T-EMS, for the (837,726) NB-LDPC code over GF(32). The proposed decoders reduce the CN area, latency, wiring between CN and Variable Node (VN) processor and the number of storage elements required in the decoder. Considering that these proposals improve both area and speed, the efficiency parameter (Mbps / Million iii NAND gates) is increased in almost five times compared to other proposals from literature.The improvements in terms of area allow us to implement NB-LDPC decoders over high-order fields which had not been possible until now due to the highcomplexity of decoders previously proposed in literature. Therefore, we present the first post-place and route report for high-rate codes over high-order fields higher than Galois Field (GF)(32). For example, for the (1536,1344) NB-LDPC code over GF (64) ResumenEn esta tesis se aborda el estudio del diseño de algoritmos de baja complejidad para la decodificación de códigos de comprobación de paridad de baja densidad no binarios (NB-LDPC) y sus correspondientes arquitecturas apropiadas para decodificar códigos de alta tasa a altas velocidades (cientos de Mbps y Gbps).En la primera parte de la tesis los principales aspectos concernientes a los códi-gos NB-LDPC s...

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A modified non-binary LDPC scheme based on watermark symbols in high speed optical transmission systems

Wang

Qiao

et al. 2016

Optics Communications

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Concatenated non-binary LDPC and HD-FEC codes for 100Gb/s optical transport systems

Cited by 9 publications

References 14 publications

A 630 Mbps non-binary LDPC decoder for FPGA

A 630 Mbps non-binary LDPC decoder for FPGA

VLSI algorithms and architectures for non-binary-LDPC decoding

A modified non-binary LDPC scheme based on watermark symbols in high speed optical transmission systems

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