This work introduces a novel serial code concatena tion (SeC) scheme to combat the error f100r problem experienced in iterated sparse graph-based error correcting codes such as turbo product (TP) codes and low density parity check (LDPC) codes. see has been widely used in the past to reduce the error f100r in iterative decoders. However, the main stumbling block for its practical application in high speed communication systems has been the need for long and complex outer codes. The use of short outer block codes with interleaving has been shown to provide a good tradeofl" between complexity and performance.Nevertheless, its application to next-generation ultra high-speed communication systems is still a major challenge as a result of the careful design of long complex interleavers needed to meet the requirements of these applications (e.g., a net coding gain > 10 dB at a bit error rate of 10-15 with an overhead of rv 20% for 100 Gb/s optical transport networks [1]). In this paper we present a new see scheme buHt from short outer block codes. Unlike previous proposals, the long interleaver is replaced by a simple block code combined with a novel encoding/decoding strategy.Based on this finding, we show that complexity and latency can be drastically reduced with negligible penalty. The see technique introduced here provides a new general framework for solving the error f100r problem induced by low-weight error patterns of any coding scheme.
I. INTRODUCTlONPowerful forward error correction (FEC) codes are needed to satisfy the requirements imposed by future high speed com munication systems. For example, net coding gains (NCGs) 2: 10dB at a bit error rate (BER) of 10-15 with an overhead (OR) as low as possible (e.g., rv 20%) are mandatory for next generation optical transport networks (OTN) [1], [2], [3]. Given their superior performance and suitability for parallel processing, large block size low density parity check (LDPC) codes and turbo product (TP) codes have been considered as FEC coding schemes for ultra-high speed transmission systems.Because of the high implementation complexity of the large block size needed to achieve high NCGs, the use of serial concatenated codes (SCC) is required when aiming at an efficient very large scale integration (VLSI). SCC schemes based on an inner LDPC or TP code with a hard-decision based outer block code have shown to be a reasonable FEC solution to (i) provide NCG2: 10dB, (ii) mitigate the well known error floor problem of LDPC and TP codes I, and (iii) I Post-processing [1] , [4] and improved decoding algorithms [5] have also been proposed to combat the error floor problem. However, their design and performance evaluation may be difficult since the knowledge of both the weight and structure of the dominant error patterns is required. reduce complexity. For instance, several SCC FEC schemes for 100 Gigabits per second (Gb/s) OTN applications have been proposed (see [2], [3] and references therein). In [2] it is experimentally shown that a 20.5% concatenated code based o...