Conceptual Review on Number Theoretic Transform and Comprehensive Review on Its Implementations

Satriawan, Ardianto; Mareta, Rella; Anshori, Isa; Shalannanda, Wervyan; Barra, Aleams

doi:10.1109/access.2023.3294446

Cited by 18 publications

(1 citation statement)

References 115 publications

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“…The Montgomery method has received less attention as it needs to be done in the "Montgomery domain". On the other hand, the Barret method is more efficient and is used more frequently in LBC cryptosystems [7]. Barrett reduction utilizes pre-computed values to approximate the division by the modulus.…”

Section: Introductionmentioning

confidence: 99%

A High-Efficiency Modular Multiplication Digital Signal Processing for Lattice-Based Post-Quantum Cryptography

Nguyen,

Pham,

Hoang

2023

Cryptography

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The Number Theoretic Transform (NTT) has been widely used to speed up polynomial multiplication in lattice-based post-quantum algorithms. All NTT operands use modular arithmetic, especially modular multiplication, which significantly influences NTT hardware implementation efficiency. Until now, most hardware implementations used Digital Signal Processing (DSP) to multiply two integers and optimally perform modulo computations from the multiplication product. This paper presents a customized Lattice-DSP (L-DSP) for modular multiplication based on the Karatsuba algorithm, Vedic multiplier, and modular reduction methods. The proposed L-DSP performs both integer multiplication and modular reduction simultaneously for lattice-based cryptography. As a result, the speed and area efficiency of the L-DSPs are 283 MHz for 77 SLICEs, 272 MHz for 87 SLICEs, and 256 MHz for 101 SLICEs with the parameters q of 3329, 7681, and 12,289, respectively. In addition, the N−1 multiplier in the Inverse-NTT (INTT) calculation is also eliminated, reducing the size of the Butterfly Unit (BU) in CRYSTAL-Kyber to about 104 SLICEs, equivalent to a conventional multiplication in the other studies. Based on the proposed DSP, a Point-Wise Matrix Multiplication (PWMM) architecture for CRYSTAL-Kyber is designed on a hardware footprint equivalent to 386 SLICEs. Furthermore, this research is the first DSP designed for lattice-based Post-quantum Cryptography (PQC) modular multiplication.

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Section: Introductionmentioning

confidence: 99%

A High-Efficiency Modular Multiplication Digital Signal Processing for Lattice-Based Post-Quantum Cryptography

Nguyen,

Pham,

Hoang

2023

Cryptography

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Point Calculation Detection System Based on In Suit Convolution Transistor for Clinical Diagnosis of Heart Disease

Cheng,

Zhang,

et al. 2024

Adv Funct Materials

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Electrocardiograph signals reflect the current state of the heart and have great significance to the clinical diagnosis of the heart. Convolutional neural networks perform excellently in electrocardiograph pattern recognition. However, CNNs processing ECG signals need to convert them from 1D to 2D, leading to additional circuit and time costs in hardware. Here, a convolution organic transistor (COT) is proposed for monitoring the ECG with CNNs. Based on the surface electric field effect and trap effect, COT can directly process 1D ECG data without complex preprocessing. It can complete the convolution calculation of ECG signals ≈20 000 times per second in theory and reduce the number of devices by 83% compared to conventional arrays. Further, actual ECG signals are measured and input into the COT, which can initially recognize the type of ECG abnormality. Finally, a point calculation detection system is established with 96.2% recognition accuracy in the five‐heartbeat classification task by combining the 1D CNN.

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Hardware architectures for computing the cosine transforms over the finite field F28$\mathbb {F}_{2^8}$

de Oliveira Neto,

Coutinho

2024

Electronics Letters

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This article presents hardware architectures for computing four types of the 8‐point cosine transforms over the finite field . The proposed architectures utilize three distinct approaches, described in SystemVerilog, and are synthesized on a field‐programmable gate array (FPGA) SoC platform. To implement the design, an improved version of a standard multiplier is presented by precomputing the required constants, thereby reducing hardware complexity. The system is integrated as a memory‐mapped Dual Core Cortex A9 peripheral to test the proposed architecture in the employed FPGA SoC. Among the three proposed architectures, one can choose to work up to 218.39 MHz, using 626 Logic Elements (LE) and 608 one‐bit registers; work up to 171 MHz, using 313 LE and 128 one‐bit registers; or work up to 197.36 MHz, at the cost of 350 LE and 293 one‐bit registers.

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Conceptual Review on Number Theoretic Transform and Comprehensive Review on Its Implementations

Cited by 18 publications

References 115 publications

A High-Efficiency Modular Multiplication Digital Signal Processing for Lattice-Based Post-Quantum Cryptography

A High-Efficiency Modular Multiplication Digital Signal Processing for Lattice-Based Post-Quantum Cryptography

Point Calculation Detection System Based on In Suit Convolution Transistor for Clinical Diagnosis of Heart Disease

Hardware architectures for computing the cosine transforms over the finite field F28$\mathbb {F}_{2^8}$

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