Concretely Mapped Symbolic Memory Locations for Memory Error Detection

Tu, Haoxin; Jiang, Lingxiao; Hong, Jiaqi; Ding, Xuhua; Jiang, He

doi:10.1109/tse.2024.3395412

IIEEE Trans. Software Eng.

2024

DOI: 10.1109/tse.2024.3395412

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Concretely Mapped Symbolic Memory Locations for Memory Error Detection

Haoxin Tu,

Lingxiao Jiang,

Jiaqi Hong

et al.

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STRIVE: Empowering a Low Power Tensor Processing Unit with Fault Detection and Error Resilience

Gundi,

Roy,

Chakraborty

2024

ACM Trans. Des. Autom. Electron. Syst.

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Rapid growth in Deep Neural Network (DNN) workloads has increased the energy footprint of the Artificial Intelligence (AI) computing realm. For optimum energy efficiency, we propose operating a DNN hardware in the Low-Power Computing (LPC) region. However, operating at LPC causes increased delay sensitivity to Process Variation (PV). Delay faults are an intriguing consequence of PV. In this paper, we demonstrate the vulnerability of DNNs to delay variations, substantially lowering the prediction accuracy. To overcome delay faults, we present STRIVE—a post-fabrication fault detection and reactive error reduction technique. We also introduce a time-borrow correction technique to ensure error-free DNN computation.

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STRIVE: Empowering a Low Power Tensor Processing Unit with Fault Detection and Error Resilience

Gundi,

Roy,

Chakraborty

2024

ACM Trans. Des. Autom. Electron. Syst.

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show abstract

scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.

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Concretely Mapped Symbolic Memory Locations for Memory Error Detection

Cited by 1 publication

References 50 publications

STRIVE: Empowering a Low Power Tensor Processing Unit with Fault Detection and Error Resilience

STRIVE: Empowering a Low Power Tensor Processing Unit with Fault Detection and Error Resilience

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