Conduction band offset of HfO2 on GaAs

Seguini, Gabriele; Perego, Michele; Spiga, S.; Fanciulli, M.; Dimoulas, A.

doi:10.1063/1.2805811

Cited by 48 publications

(17 citation statements)

References 20 publications

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“…The charging behavior of the GeO 2 /Ge stack by XPS was also consistent with recent XPS and IPE investigations on GaAs/high-k, HfO 2 /Si, and HfO 2 /SiO 2 /Si stacks. [18][19][20]27 We also note that the CBO value obtained here show excellent consistence with the theoretical calculation at a GeO 2 /Ge interface constructed by amorphous GeO 2 connected to crystalline Ge through a substoichiometric oxide region with regular structural parameters using a mixed hybrid density functionals, 14 indicating a true CBO value larger than 1.5 eV at the GeO 2 /Ge interface with low density of interface defect traps. As for the scattering of reported CBO values (Table I), artifacts caused by charging for XPS characterization has been proved to be a crucial factor here.…”

supporting

confidence: 81%

Conduction band offset at GeO2/Ge interface determined by internal photoemission and charge-corrected x-ray photoelectron spectroscopies

Zhang

Nishimula

Nagashio

et al. 2013

Applied Physics Letters

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We report a consistent conduction band offset (CBO) at a GeO2/Ge interface determined by internal photoemission spectroscopy (IPE) and charge-corrected X-ray photoelectron spectroscopy (XPS). IPE results showed that the CBO value was larger than 1.5 eV irrespective of metal electrode and substrate type variance, while an accurate determination of valence band offset (VBO) by XPS requires a careful correction of differential charging phenomena. The VBO value was determined to be 3.60 ± 0.2 eV by XPS after charge correction, thus yielding a CBO (1.60 ± 0.2 eV) in excellent agreement with the IPE results. Such a large CBO (>1.5 eV) confirmed here is promising in terms of using GeO2 as a potential passivation layer for future Ge-based scaled CMOS devices.

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supporting

confidence: 81%

Conduction band offset at GeO2/Ge interface determined by internal photoemission and charge-corrected x-ray photoelectron spectroscopies

Zhang

Nishimula

Nagashio

et al. 2013

Applied Physics Letters

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“…The sample without HCl clean shows a lower threshold ⌽ e ͑IL͒ = 2.3Ϯ 0.1 eV, which is close to the previously reported threshold for electron IPE from the GaAs VB into the CB of the Ga 2 O 3 IL in GaAs/ Ga 2 O 3 / GaGdO x structures 7 as well as to the spectral threshold found for atomic-beam grown HfO 2 on GaAs. 5 To conclude, we found both HfO 2 and Al 2 O 3 to provide CB and VB offsets at their interfaces with GaAs of around 2 eV, which make these material suitable for gate insulation. The problem actually resides with the IL providing only a 0.9 eV CB offset at the interface: formation of such IL due to oxidation of GaAs in the course of high-oxide deposition may lead to enhanced charge injection from GaAs into the insulating stack.…”

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confidence: 97%

“…Therefore, formation of an oxide interlayer ͑IL͒ may lead to low interface energy barriers and high leakage current, as long known for anodic oxide on GaAs. 4 Recently, low energy barriers have been reported between the GaAs valence band ͑VB͒ and the conduction band ͑CB͒ of HfO 2 grown using the atomic-beam technique 5 or ALD Al 2 O 3 :…”

mentioning

confidence: 99%

Energy barriers at interfaces of (100)GaAs with atomic layer deposited Al2O3 and HfO2

Afanasʼev

Badylevich

Stesmans

et al. 2008

Applied Physics Letters

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“…VBO is accurately predicted by reference potential method [62,63]. In the interface O9/Ga4, VBO is 1.81 eV compared to experimental data of 2.00 [64], 2.10 [65], and 2.85 eV [66]. The variation in VBOs indicates experimental samples diversity, and the VBO difference between theoretical prediction and experimental measurement results from the variety of the interfacial oxygen concentration.…”

Section: Sulfur Passivation Effect On Hfo 2 /Gaas Interfacementioning

confidence: 91%

Theoretical Progress on GaAs (001) Surface and GaAs/High‐ k Interface

Wang

Xiong

Wallace

et al. 2012

High‐k Gate Dielectrics for CMOS Technology

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The recent resurgence of interest in III-V transistor channel materials has come about due to the scaling requirement of Si-based metal oxide semiconductor (MOS) devices [1]. III-V channel materials have much higher bulk electron mobilities than Si (see Table 13.1) and thus expected to provide high channel injection velocities. Among the III-V compounds, gallium arsenide (GaAs) is a prototype material because of its many advantages, such as, 5Â higher electron mobility than Si, the availability of semiinsulating GaAs substrates, and a higher breakdown field over Si to achieve GaAs-based high-speed devices.Nevertheless, III-V materials suffer from a lack of thermodynamically stable gate dielectrics [2], with an acceptable low density of III-V/dielectric interface states, which makes it very difficult to be implemented into future CMOS-type devices. The interfacial density of states (D it ) leads to many problems such as Fermi-level pinning, reduced electron mobility, and instability of device operations. The Fermi-level pinning results in the loss of the modulation of the carrier concentration at the oxide/III-V interface by the gate bias. For oxide/III-V interfaces, the interfacial group III-or V-dangling bonds are partially saturated [3] and they can hardly be fully saturated to obtain a superior high-k/III-V interface with low D it . Furthermore, the partially saturated bonds can induce mid-gap states that lead to Fermi-level pinning. This pinning is most likely due to the presence of III(V)-O bonds and the resultant structural disorders. Therefore, understanding the oxidation and passivation mechanisms of the III-V surface are very useful to gain an important insight to control the quality of high-k/III-V interfaces [4][5][6][7][8].When high-k oxides are deposited upon III-V materials, the III-V/high-k oxide interfaces are much more complicated than the ideal III-V surface alone. The low electronic quality of an III-V/dielectric interface can be attributed to several reasons.High-k Gate Dielectrics for CMOS Technology, First Edition. Edited by Gang He and Zhaoqi Sun.

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Conduction band offset of HfO2 on GaAs

Cited by 48 publications

References 20 publications

Conduction band offset at GeO2/Ge interface determined by internal photoemission and charge-corrected x-ray photoelectron spectroscopies

Conduction band offset at GeO2/Ge interface determined by internal photoemission and charge-corrected x-ray photoelectron spectroscopies

Energy barriers at interfaces of (100)GaAs with atomic layer deposited Al2O3 and HfO2

Theoretical Progress on GaAs (001) Surface and GaAs/High‐ k Interface

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