Configurable cache tuning with a victim cache

Navarro, Osvaldo; Leiding, Tim; Hübner, Michael

doi:10.1109/recosoc.2015.7238080

Cited by 10 publications

(2 citation statements)

References 14 publications

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“…The cache tuning algorithm/heuristic can result in time and energy overheads, since the processor must stall during the tuning process. Much previous work (e.g., [2], [33], [36], [71], [104]) have proposed different algorithms/heuristics for cache tuning to minimize the potential of overhead and maximize the cache tuning benefits. These works offer a valuable foundation for IoT microprocessors.…”

Section: A Configurable/adaptable Architecturesmentioning

confidence: 99%

“…In-memory processing-or processing in memory-has been studied in relation to big data and distributed com- [27], [28], [33], [36], [53], [71], [104] Distributed heterogeneous architectures Extensibility, efficiency, future-proof [56], [68], [88] Energy harvesting and non-volatile processors Efficiency [18], [31], [35], [60], [62], [77], [97], [22], [63], [65], [72], [92], [99], [102], [108] Approximate computing Efficiency [21], [26], [38], [42], [54], [64], [81], [96], [17], [55], [58], [82], [86], [87] In-memory processing Efficiency, extensibility [5], [24], [41], [44]- [46], [103], [105] Secure microarchitectures Security …”

Section: E In-memory Processingmentioning

confidence: 99%

See 1 more Smart Citation

Microprocessor Optimizations for the Internet of Things: A Survey

Adegbija

Rogacs

Patel

et al. 2018

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-The Internet of Things (IoT) refers to a pervasive presence of interconnected and uniquely identifiable physical devices. These devices' goal is to gather data and drive actions in order to improve productivity, and ultimately reduce or eliminate reliance on human intervention for data acquisition, interpretation and use. The proliferation of these connected low-power devices will result in a data explosion that will significantly increase data transmission costs with respect to energy consumption and latency. Edge computing reduces these costs by performing computations at the edge nodes, prior to data transmission, to interpret and/or utilize the data. While much research has focused on the IoT's connected nature and communication challenges, the challenges of IoT embedded computing with respect to device microprocessors has received much less attention. This article explores IoT applications' execution characteristics from a microarchitectural perspective and the microarchitectural characteristics that will enable efficient and effective edge computing. To tractably represent a wide variety of next-generation IoT applications, we present a broad IoT application classification methodology based on application functions, to enable quicker workload characterizations for IoT microprocessors. We then survey and discuss potential microarchitectural optimizations and computing paradigms that will enable the design of right-provisioned microprocessors that are efficient, configurable, extensible, and scalable. Our work provides a foundation for the analysis and design of a diverse set of microprocessor architectures for next-generation IoT devices.

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