Configurable Floating‐Point FFT Accelerator on FPGA Based Multiple‐Rotation CORDIC

Chen, Jian-Zhang; Lei, Yuanwu; Peng, Yuanxi; He, Tingting; Deng, Ziye

doi:10.1049/cje.2016.08.002

Cited by 20 publications

(7 citation statements)

References 15 publications

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“…Much work has been focused on reducing memory demands. Computing twiddle factors on-chip has been explored [33,35,62] and applied in industry [90]. In-memory FFT accelerators have also been proposed to reduce this communication overhead [36,81,138] along with 3D-stacked memory accelerators [60].…”

Section: Fft Acceleratorsmentioning

confidence: 99%

Bind the gap: compiling real software to hardware FFT accelerators

Woodruff

Armengol-Estapé

Ainsworth

et al. 2022

Proceedings of the 43rd ACM SIGPLAN International Conference on Programming Language Design and Implementation

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Specialized hardware accelerators continue to be a source of performance improvement. However, such specialization comes at a programming price. The fundamental issue is that of a mismatch between the diversity of user code and the functionality of fixed hardware, limiting its wider uptake.Here we focus on a particular set of accelerators: those for Fast Fourier Transforms. We present FACC (Fourier ACcelerator Compiler), a novel approach to automatically map legacy code to Fourier Transform accelerators. It automatically generates drop-in replacement adapters using Input-Output (IO)-based program synthesis that bridge the gap between user code and accelerators. We apply FACC to unmodified GitHub C programs of varying complexity and compare against two existing approaches. We target FACC to a high-performance library, FFTW, and two hardware accelerators, the NXP PowerQuad and the Analog Devices FFTA, and demonstrate mean speedups of 9x, 17x and 27x respectively.

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Section: Fft Acceleratorsmentioning

confidence: 99%

Bind the gap: compiling real software to hardware FFT accelerators

Woodruff

Armengol-Estapé

Ainsworth

et al. 2022

Proceedings of the 43rd ACM SIGPLAN International Conference on Programming Language Design and Implementation

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“…In FMCW radar, Q-noise accumulates because the FFT is repeatedly performed during signal processing. Therefore, many studies have proposed designing and implementing the FFT processor using a floating-point operator [ 15 , 16 , 17 , 18 , 19 ].…”

Section: Introductionmentioning

confidence: 99%

FPGA Implementation of an Efficient FFT Processor for FMCW Radar Signal Processing

Heo

Jung

Lee

et al. 2021

Sensors

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This paper presents the design and implementation results of an efficient fast Fourier transform (FFT) processor for frequency-modulated continuous wave (FMCW) radar signal processing. The proposed FFT processor is designed with a memory-based FFT architecture and supports variable lengths from 64 to 4096. Moreover, it is designed with a floating-point operator to prevent the performance degradation of fixed-point operators. FMCW radar signal processing requires windowing operations to increase the target detection rate by reducing clutter side lobes, magnitude calculation operations based on the FFT results to detect the target, and accumulation operations to improve the detection performance of the target. In addition, in some applications such as the measurement of vital signs, the phase of the FFT result has to be calculated. In general, only the FFT is implemented in the hardware, and the other FMCW radar signal processing is performed in the software. The proposed FFT processor implements not only the FFT, but also windowing, accumulation, and magnitude/phase calculations in the hardware. Therefore, compared with a processor implementing only the FFT, the proposed FFT processor uses 1.69 times the hardware resources but achieves an execution time 7.32 times shorter.

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“…Supriya et al [16] present reconfigurable coordinate rotation digital computer (CORDIC) based on rotating, vectoring mode for circular and hyperbolic trajectory. The designs use more coordinate calculation unit for recursive and pipelined architecture in both the modes of the CORDIC, which consumes more chip area.Chen et al [17] present multiple rotation CORDIC for configurable fast fourier transform (FFT) accelerator, the FFT twiddle factors calculation based on the CORDIC rotation, which saves the hardware cost and CORDIC model designed using compression iteration with four rotations, twiddles direction prediction and segmented parallel iteration. However, this process utilizes much time in the FFT process.…”

Section: Introductionmentioning

confidence: 99%

Design and analysis of optimized CORDIC based GMSK system on FPGA platform

Kajur

Prasad²

2020

IJECE

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The Gaussian minimum shift keying (GMSK) is one of the best suited digital modulation schemes in the global system for mobile communication (GSM) because of its constant envelop and spectral efficiency characteristics. Most of the conventional GMSK approaches failed to balance the digital modulation with efficient usage of spectrum. In this article, the hardware architecture of the optimized CORDIC-based GMSK system is designed, which includes GMSK Modulation with the channel and GMSK Demodulation. The modulation consists of non-return zero (NRZ) encoder, an integrator followed by Gaussian filtering and frequency modulation (FM). The GMSK demodulation consists of FM demodulator, followed by differentiation and NRZ decoder. The FM Modulation and demodulation use the optimized CORDIC model for an In-phase (I) and quadrature (Q) phase generation. The optimized CORDIC is designed by using quadrant mapping and pipelined structure to improve the hardware and computational complexity in GMSK systems. The GMSK system is designed on the Xilinx platform and implemented on Artix-7 and Spartan-3EFPGA. The hardware constraints like area, power, and timing utilization are summarized. The comparison of the optimized CORDIC model with similar CORDIC approaches is tabulated with improvements.

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Configurable Floating‐Point FFT Accelerator on FPGA Based Multiple‐Rotation CORDIC

Cited by 20 publications

References 15 publications

Bind the gap: compiling real software to hardware FFT accelerators

Bind the gap: compiling real software to hardware FFT accelerators

FPGA Implementation of an Efficient FFT Processor for FMCW Radar Signal Processing

Design and analysis of optimized CORDIC based GMSK system on FPGA platform

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