Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays 2018
DOI: 10.1145/3174243.3174250
|View full text |Cite
|
Sign up to set email alerts
|

Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1
1
1

Citation Types

0
17
0

Year Published

2019
2019
2023
2023

Publication Types

Select...
5
2

Relationship

0
7

Authors

Journals

citations
Cited by 19 publications
(18 citation statements)
references
References 5 publications
0
17
0
Order By: Relevance
“…Recent high-performance FPGAs are shown to support a throughput of nearly 1 Tbps. 21 The FPGA is highly agile and meets most of the programmable switch ASIC requirements. However, it cannot be used for high-speed routing due to inherent limitations in realizing a large size content addressable memory.…”
Section: Pdp and P4mentioning
confidence: 99%
See 1 more Smart Citation
“…Recent high-performance FPGAs are shown to support a throughput of nearly 1 Tbps. 21 The FPGA is highly agile and meets most of the programmable switch ASIC requirements. However, it cannot be used for high-speed routing due to inherent limitations in realizing a large size content addressable memory.…”
Section: Pdp and P4mentioning
confidence: 99%
“…A reconfigurable packet parser that handles more than 1 Tbps is demonstrated based on an FPGA showcases the I/O processing capability of the FPGA. 21 While such capability is available, adding TCAM lookup resources to FPGA is required before positioning alternate hardware as a full-fledged network switch. Simplified I/O processing can enable the use of alternate hardware as a replacement of network switch.…”
Section: Network Use Casesmentioning
confidence: 99%
“…A new parser architecture is presented by Jakub et al in [21], which is capable to currently scale up to a terabit throughput in a Xilinx UltraScale+ FPGA, and the overall processing speed is sustained even on the shortest frame lengths. Its main method is building a protocol process module pool, and multiple packets are processed in parallel in this pool.…”
Section: Packet Parser Solutionsmentioning
confidence: 99%
“…There are countless papers in which FPGA-based parsers are proposed. [9], [10], [11], [12] and [13] are just a few examples of such research efforts which achieve throughput on the scale of hundreds of Gigabits per second. However, it should be noted that these architectures achieve this throughput by means of operating on ultra-wide input due to their low frequencies.…”
Section: Introductionmentioning
confidence: 99%