Configurable MBIST Processor for Embedded Memories Testing

Wojciechowski, Andrzej; Marcinek, Krzysztof; Pleskacz, Witold A.

doi:10.23919/mixdes.2019.8787161

Cited by 9 publications

(6 citation statements)

References 7 publications

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“…Table 3. The notations in the memory testing algorithms [18], [46]- [48] Symbol Description ↑ or ⇑ address sequence changes in ascending order ↓ or ⇓ address sequence changes in descending order ↕ or ⇕ address sequence can change either way R0 read operation (reading a 0 from a cell) R1 read operation (reading a 1 from a cell) W0…”

Section: Memory Testing Algorithmsmentioning

confidence: 99%

A review paper on memory fault models and test algorithms

Jidin

Hussin

Fook³

et al. 2021

Bulletin EEI

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Testing embedded memories in a chip can be very challenging due to their high-density nature and manufactured using very deep submicron (VDSM) technologies. In this review paper, functional fault models which may exist in the memory are described, in terms of their definition and detection requirement. Several memory testing algorithms that are used in memory built-in self-test (BIST) are discussed, in terms of test operation sequences, fault detection ability, and also test complexity. From the studies, it shows that tests with 22 N of complexity such as March SS and March AB are needed to detect all static unlinked or simple faults within the memory cells. The N in the algorithm complexity refers to Nx*Ny*Nz whereby Nx represents the number of rows, Ny represents the number of columns and Nz represents the number of banks. This paper also looks into optimization and further improvement that can be achieved on existing March test algorithms to increase the fault coverage or to reduce the test complexity.

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Section: Memory Testing Algorithmsmentioning

confidence: 99%

A review paper on memory fault models and test algorithms

Jidin

Hussin

Fook³

et al. 2021

Bulletin EEI

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show abstract

“…Demand for high-speed, highly integrated, low-power memory is growing unprecedentedly because cloud computing, artificial intelligence, and fifthgeneration (5G) communications, among others, are positioned as the main directions of the fourth Industrial Revolution. To ensure the characteristics of modern memory of computer systems that meet the requirements of new technological advances, the necessity and importance of testing memory devices have increased sufficiently [1,2]. The main task of memory testing is to detect faulty states described by various models of their failures [3][4][5].…”

Section: Introductionmentioning

confidence: 99%

Linked Coupling Faults Detection by Multirun March Tests

Mrozek,

Yarmolik

2024

Applied Sciences

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This paper addresses the problem of describing the complex linked coupling faults of memory devices and formulating the necessary and sufficient conditions for their detection. The main contribution of the proposed approach is based on using a new formal model of such faults, the critical element of which is the introduction of roles and scenarios performed by the cells involved in the fault. Three roles are defined such that the cells of the complex linked coupling faults perform, namely, the roles of the aggressor (A), the victim (V), and both (B), performed by two cells simultaneously in relation to each other. The memory march test and applied address sequence and background determine the scenario for implementing the roles of memory faulty cells. The necessary and sufficient conditions for detecting linked coupling faults are given based on a new formal model. Formally, the undetectable linked coupling faults are defined, and the conditions for their detection are formulated using multirun memory march tests. The experimental investigation confirmed the validity of the proposed formulated statements. Based on the example of a linked coupling fault, this study demonstrates the fulfillment of the necessary and sufficient conditions for its detection using a single march test. As demonstrated in this article, employing the approach proposed by the authors, a two-pass march C test, for instance, enables the attainment of 55.42% fault coverage for linked coupling faults, inclusive of undetectable faults identified by the single-pass march test.

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“…The first stage is examined the failure identified by the memory built-in self-test controller through the test of repairing memory. The second stage determines the repair signature to repair memory [6,7]. Each repairable memory has repair registers, which hold the repair signature.…”

Section: Introductionmentioning

confidence: 99%

Deep Q-Learning with Bit-Swapping-Based Linear Feedback Shift Register fostered Built-In Self-Test and Built-In Self-Repair for SRAM

Ahmed

Alnatheer

2022

Micromachines

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Including redundancy is popular and widely used in a fault-tolerant method for memories. Effective fault-tolerant methods are a demand of today’s large-size memories. Recently, system-on-chips (SOCs) have been developed in nanotechnology, with most of the chip area occupied by memories. Generally, memories in SOCs contain various sizes with poor accessibility. Thus, it is not easy to repair these memories with the conventional external equipment test method. For this reason, memory designers commonly use the redundancy method for replacing rows–columns with spare ones mainly to improve the yield of the memories. In this manuscript, the Deep Q-learning (DQL) with Bit-Swapping-based linear feedback shift register (BSLFSR) for Fault Detection (DQL-BSLFSR-FD) is proposed for Static Random Access Memory (SRAM). The proposed Deep Q-learning-based memory built-in self-test (MBIST) is used to check the memory array unit for faults. The faults are inserted into the memory using the Deep Q-learning fault injection process. The test patterns and faults injection are controlled during testing using different test cases. Subsequently, fault memory is repaired after inserting faults in the memory cell using the Bit-Swapping-based linear feedback shift register (BSLFSR) based Built-in Self-Repair (BISR) model. The BSLFSR model performs redundancy analysis that detects faulty cells, utilizing spare rows and columns instead of defective cells. The design and implementation of the proposed BIST and Built-in Self-Repair methods are developed on FPGA, and Verilog’s simulation is conducted. Therefore, the proposed DQL-BSLFSR-FD model simulation has attained 23.5%, 29.5% lower maximum operating frequency (minimum clock period), and 34.9%, 26.7% lower total power consumption than the existing approaches.

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Configurable MBIST Processor for Embedded Memories Testing

Cited by 9 publications

References 7 publications

A review paper on memory fault models and test algorithms

A review paper on memory fault models and test algorithms

Linked Coupling Faults Detection by Multirun March Tests

Deep Q-Learning with Bit-Swapping-Based Linear Feedback Shift Register fostered Built-In Self-Test and Built-In Self-Repair for SRAM

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