Configuration Memory Scrubbing of SRAM-Based FPGAs Using a Mixed 2-D Coding Technique

Vlagkoulis, Vasileios; Sari, Aitzan; Antonopoulos, G.; Psarakis, Mihalis; Tavoularis, Antonios; Furano, Gianluca; Boatella-Polo, Cesar; Poivey, C.; Ferlet-Cavrois, V.; Kastriotou, Maria; Martinéz, P. Fernandéz; Alía, Rubén García

doi:10.1109/tns.2022.3151977

Cited by 10 publications

(2 citation statements)

References 24 publications

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“…Although storage and security performance are important, private-preserving block-level deduplication of multimedia content is still frequently disregarded [24]. The proposed frame level deduplication system improves deduplication efficiency by performing deduplication not only on the units of a single video, but also on the blocks of similar content videos [25].…”

Section: Proposed Methodsmentioning

confidence: 99%

Efficient Memory Handling Model with Consistent Video Frame Duplication Removal with Precise Compression

Sameerunnisa,

Jabez

2023

RIA

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Massive amounts of videos are being made and shared online as mobile devices and social networks gain popularity in recent years. The enormous expansion in the amount of video data created has made storing and quickly searching it all quite difficult. Because many movies are duplicates or near-duplicates in practice, recognizing these copies has become a critical strategy for decreasing the amount of storage with duplicate removal models. Video compression is an important part of Internet video delivery for efficient memory management. Deep learning's growth has sparked a revival in video compression, with many frameworks offering comparable or even higher performance than traditional video codecs presented in recent years. Despite the advancement in rate-distortion, these models are substantially slower and need more memory, limiting their practical application. The exponentially increasing volume of video data created has presented enormous problems to video deduplication technologies. People are interested in uploading and sharing information in photo and video formats in this digital era. This expansion has resulted in increased storage capacity, which contains a large amount of redundant multimedia material. Many deduplication algorithms are being rapidly developed nowadays, although they are often slow and have rather imprecise identification processes. Deduplication is one of the emerging ways for coping with redundant data stored in several locations. When more than a copy of the same data is detected, a single copy is preserved, and the other data is replaced by pointers pointing to the preserved copy and also duplicate frames will be removed by segmenting the video for memory efficiency. Storage can be utilised to effectively store a large amount of other data. While there are many other types of deduplication algorithms, picture and video deduplication strategies and implementations receive a lot of attention since they are difficult to implement. In this research a Consistent Video Frame Duplication Removal with Precise Compression (CVFDR-PC) model for efficient memory handling is proposed. This research provides a versatile and efficient video frame deduplication framework with compression model that effectively handles the memory. The proposed model when contrasted with the existing methods exhibit better performance levels.

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Section: Proposed Methodsmentioning

confidence: 99%

Efficient Memory Handling Model with Consistent Video Frame Duplication Removal with Precise Compression

Sameerunnisa,

Jabez

2023

RIA

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“…viewpoint of the implemented design, as they may lead to open lines, shortcircuits, delays, and permanent changes in the combinational logic of the circuit. Once affected by SEUs, CM cells remain faulty until partially or fully reprogrammed to fix the problem, using scrubbing techniques [2], or to implement another circuit. This problem becomes critical in high-radiation environments [3] [4], where upset rates may exceed the terrestrial conditions by orders of magnitude.…”

Section: Introductionmentioning

confidence: 99%

Reversing FPGA architectures for speeding up fault injection: does it pay?

Tuzov

Andrés

Ruíz

2022

2022 18th European Dependable Computing Conference (EDCC)

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Although initially considered for fast system prototyping, Field Programmable Gate Arrays (FPGAs) are gaining interest for implementing final products thanks to their inherent reconfiguration capabilities. As they are susceptible to soft errors in their configuration memory, the dependability of FPGA-based designs must be accurately evaluated to be used in critical systems. In recent years, research has focused on speeding up fault injection in FPGA-based systems by parallelising experimentation, reducing the injection time, and decreasing the number of experiments. Going a step further requires delving into the FPGA architecture, i.e. precisely determining which components are implementing the considered design (mapping) and which are exercised by the considered workload (profiling). After that, fault injection campaigns can focus on those components actually used to identify critical ones, i.e. those leading the target system to fail. Some manufacturers, like Xilinx, identify those bits in the FPGA configuration memory that may change the implemented design when affected by a soft error. However, their correspondence to particular components of the FPGA fabric and their relationship with the implementation-level model are yet unknown. This paper addresses whether the effort of reversing an FPGA architecture to filter out redundant and unused essential bits pays in terms of experimental time. Since the work of reversing the complete architecture of an FPGA is titanic, as the first step towards this ambitious goal, this paper focuses on those elements in charge of implementing the combinational logic of the design (Look-Up Tables). The experimental results that support this study derive from implementing three soft-core processors on a Zynq SoC FPGA and show the interest of the proposal.

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Secure Quantum‐based Adder Design for Protecting Machine Learning Systems Against Side‐Channel Attacks

Ain,

Ahmadpour,

Navimipour

et al. 2025

Applied Soft Computing

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Configuration Memory Scrubbing of SRAM-Based FPGAs Using a Mixed 2-D Coding Technique

Cited by 10 publications

References 24 publications

Efficient Memory Handling Model with Consistent Video Frame Duplication Removal with Precise Compression

Efficient Memory Handling Model with Consistent Video Frame Duplication Removal with Precise Compression

Reversing FPGA architectures for speeding up fault injection: does it pay?

Secure Quantum‐based Adder Design for Protecting Machine Learning Systems Against Side‐Channel Attacks

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