Congestion-aware topology optimization of structured power/ground networks

Singh, Jaskirat; Sapatnekar, Sachin S.

doi:10.1109/tcad.2005.846369

Cited by 29 publications

(24 citation statements)

References 24 publications

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“…This adversely affects the run time of the design procedure as in each iteration, following a pitch decrease in any one of the active partitions, it is necessary to construct the global matrix £ , whose dimensions are rapidly increasing which leads to increase in number of conjugate gradient steps to solve the global system. To overcome this problem, we employ the port approximation technique suggested in [6] to reduce the macromodel sizes. By this approach, some of the port nodes located on the partition wires are collapsed.…”

Section: ) First Level Of Partitioningmentioning

confidence: 99%

“…Typically, the choices available to a supply net designer are to (i) appropriately size the supply net wires [1][2][3][4], (ii) perform topology optimization, i.e., to assign suitable pitches to the power grid wires and/or determine the optimal assignment of the pins to the pads and placement of pads on the power grid [5][6][7][8][9], and (iii) add decoupling capacitors [10], [11].…”

Section: Introductionmentioning

confidence: 99%

“…Schemes for automated power distribution network design can be divided into the following two categories, based on tradeoffs between the accuracy of the embedded power grid simulator and the level of sophistication of the optimizer: (A) Heuristic iterative optimization methods, employing an explicit and exact circuit analysis step in the main optimization loop to determine constraint violations in the power grid [6], [10].…”

Section: Introductionmentioning

confidence: 99%

“…The method employs an iterative scheme of recursively partitioning the chip area and constructing the power grid locally in the partitions by adjusting the wire pitches and the widths. The power grids constructed by our design procedure have a locally regular, globally irregular structure [6]. The grids within a partition are constructed to be uniform, i.e., they have the same wire width and wire pitch, but power grid wires in different partitions may have different widths and pitches, as determined by the current density requirements of the underlying functional blocks.…”

Section: Introductionmentioning

confidence: 99%

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Partition-based algorithm for power grid design using locality

Singh

Sapatnekar

2006

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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This paper presents an efficient heuristic algorithm, which employs a successive partitioning and grid refinement scheme, for designing the power distribution network of a chip. In our iterative procedure, the chip area is recursively bipartitioned, and the wire pitches and the wire widths of the power grid in the partitions are repeatedly adjusted to meet the voltage drop and current density specifications. By using the macromodels of the power grid constructed in the previous levels of partitioning, the scheme ensures that a small global power grid system is simulated in each iteration. The idea is based on the notion that due to the locality properties of the power grid, the effects of distant nodes and sources can be modeled more coarsely than nearby elements, and includes practical methods that enhance the convergence of the iterative conjugate-gradient based solution engine that is used in each step. Finally, a post-processing step at the end of the optimization is employed to maximize the alignment of wires in adjacent partitions. The effectiveness of the scheme is demonstrated by designing various power grids with real circuit parameters and realistic input current values. The proposed algorithm is able to design power grids comprising thousands of wires and more than a million electrical nodes in about 6 to 13 minutes. When compared to a multigrid-based power grid design scheme, it is found to save about 7% to 12% of wire area, and on an average is 14% faster.

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Section: ) First Level Of Partitioningmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Partition-based algorithm for power grid design using locality

Singh

Sapatnekar

2006

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…This assumption is not true anymore in many cases. Power grid networks which supply elements of large circuits with energy are of this special form [23,26]. Often these power grids are realized as an extra layer of elements in between the layers of transistors.…”

Section: Introductionmentioning

confidence: 99%

On Stability, Passivity and Reciprocity Preservation of ESVDMOR

Benner

Schneider

2011

Lecture Notes in Electrical Engineering

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The reduction of parasitic linear subcircuits is one of many issues in model order reduction (MOR) for VLSI design. This issue is well explored, but recently the incorporation of subcircuits from different modelling sources into the circuit model has led to new structural aspects: so far, the number of elements in the subcircuits was significantly larger than the number of connections to the whole circuit, the so called pins or terminals. This assumption is no longer valid in all cases such that the simulation of these circuits or rather the reduction of the model requires new methods. In [6,15,17], the extended singular value decomposition based model order reduction (ESVDMOR) algorithm is introduced as a way to handle this kind of circuits with a massive number of terminals. Unfortunately, the ESVDMOR approach has some drawbacks because it uses the SVD for matrix factorizations. In [5,22] the truncated SVD (TSVD) as an alternative to the SVD within the ESVDMOR is introduced. In this paper we show that ESVDMOR as well as the modified approach is stability, passivity, and reciprocity preserving under reasonable assumptions.

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Efficient power pad assignment for multi‐voltage SoC and its application in floorplanning

Chu

Xia

Wang

et al. 2015

Circuit Theory & Apps

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Multi-voltage techniques are being developed to improve power savings by providing lower supply voltages for noncritical blocks under the performance constraint. However, the resulted lower voltage drop noise margin brings serious obstacles in power/ground (P/G) network design of the wire-bonding package. For voltage drop optimization, both block and power pad positions are important factors that need to be considered. Traditional multi-voltage floorplanning methods use rough estimation to evaluate the P/G network resource without considering the locations of power pads. To remedy this deficiency, in this paper, an efficient voltage drops aware power pad assignment (PPA) method is proposed, and it is further integrated into a floorplanning algorithm. We first present a fast PPA method for each power domain by the spring model. Then, to evaluate voltage drops during floorplanning iterations, the weighted distance from the blocks to the power pads is adopted as an optimization objective instead of time-consuming matrix computation. Experimental results on Gigascale System Research Center (GSRC) benchmark circuits indicate that the proposed method generates an optimized placement of power pads and floorplanning of blocks with high efficiency.decoupling capacitors configuration to alleviate the power delivery noise [12,13]. However, those techniques are implemented only when the floorplan or placement is ready. With exploding design complexity, it is necessary to consider voltage drop issues in the early design cycle [14][15][16][17]. Once the voltage drops aware floorplan is obtained, the detailed P/G network design can be performed in the subsequent placement and routing stages that consider Steiner tree construction and electromigration issues [18,19].It is reported that 5% of voltage decrease may cause the circuit performance slowdown up to 15% or more [20]. Hence, designers typically limit the voltage drops within 10% of the supply voltage to guarantee faultless operation [21]. Lower supply voltage indicates that lower noise margins or smaller voltage drops are permitted on the P/G network [22]. For instance, 1.5-V supply voltages permit 150-mV voltage drop while 1.0-V supply voltages only allow 100-mV voltage drop. Compared with single-voltage SoC, the voltage drop constraints present more challenges for the P/G network design of the multi-voltage SoC. First, from a low-power perspective, a VI with a larger area and a lower supply voltage is preferred during the VI generation process. However, the permitted ultra-low voltage drops make the P/G network hard to design. Second, power pads are located at the periphery of the chip for wire-bonding package. Locations of power pads affect both the timing and voltage drops [23]. Although multiple power pads for each VI can leverage the voltage drops, it may not be practical because the power pads must compete with other signal I/Os under the limited pad resource. Thus, it is vital to consider voltage drops in P/G network design for multi-voltage SoC. Related workConsid...

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Congestion-aware topology optimization of structured power/ground networks

Cited by 29 publications

References 24 publications

Partition-based algorithm for power grid design using locality

Partition-based algorithm for power grid design using locality

On Stability, Passivity and Reciprocity Preservation of ESVDMOR

Efficient power pad assignment for multi‐voltage SoC and its application in floorplanning

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