Partition-based algorithm for power grid design using locality

Abstract

This paper presents an efficient heuristic algorithm, which employs a successive partitioning and grid refinement scheme, for designing the power distribution network of a chip. In our iterative procedure, the chip area is recursively bipartitioned, and the wire pitches and the wire widths of the power grid in the partitions are repeatedly adjusted to meet the voltage drop and current density specifications. By using the macromodels of the power grid constructed in the previous levels of partitioning, the scheme ensures that a small global power grid system is simulated in each iteration. The idea is based on the notion that due to the locality properties of the power grid, the effects of distant nodes and sources can be modeled more coarsely than nearby elements, and includes practical methods that enhance the convergence of the iterative conjugate-gradient based solution engine that is used in each step. Finally, a post-processing step at the end of the optimization is employed to maximize the alignment of wires in adjacent partitions. The effectiveness of the scheme is demonstrated by designing various power grids with real circuit parameters and realistic input current values. The proposed algorithm is able to design power grids comprising thousands of wires and more than a million electrical nodes in about 6 to 13 minutes. When compared to a multigrid-based power grid design scheme, it is found to save about 7% to 12% of wire area, and on an average is 14% faster.

Multi-Layer Interdigitated Power Distribution Networks

“…The current density of an arbitrary layer is (12) where and are the current and cross section of layer , respectively. The skin effect is considered in determining the cross-section of the layer, (13) (14) (15) where is the skin depth. The skin depth is defined as (16) where is the conductivity of the material.…”

“…To overcome this issue, several algorithms based on different optimization techniques have been developed [13], [14]; however, only the package inductance is considered [14], neglecting the on-chip inductance. An algorithm based on partitioning the P/G network into smaller sections is proposed in [15], where voltage drops are considered. With more advanced packaging techniques (such as flip-chip), the on-chip inductive noise is also important [1], [16].…”

Variability and Statistical Design

“…Effective techniques for optimization include pin assignment 75), 104) , topology optimization 77), 78) , wire sizing 85), 86) , and decoupling capacitor (decap) insertion 87) . The last of these deliberately inserts capacitors into the power grid: these act as charge reservoirs that damp down the effects of fast transients by providing a nearby source of charge to feed the current drawn by the functional blocks.…”

Effective Resistance of a Two Layer Mesh

“…An on-chip power and ground distribution network is commonly modeled as a resistive mesh structure with different vertical and horizontal unit resistances, as shown in Fig. 1(a) [1]- [4], where the thickness and width of the metal lines are typically different in orthogonal metal layers. Power and ground networks are illustrated in Fig.…”