Congestion driven quadratic placement

Parakh, P.N.; Brown, R.B.; Sakallah, K.A.

doi:10.1109/dac.1998.724481

Cited by 17 publications

(16 citation statements)

References 7 publications

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“…Indeed, in variable-die layout one can always add routing tracks to complete routing at the cost of increased area [15], but this is impossible with a fixed outline. To improve congestion, it is common to use cell-bloating (i.e., treating cells as if they were larger in order to free routing tracks around them) in congested regions.…”

Section: Fixed-die Placement In Physical Synthesismentioning

confidence: 99%

On whitespace and stability in mixed-size placement and physical synthesis

Adya

Markov

Villarrubia

2003

ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)

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In the context of physical synthesis, large-scale standard-cell placement algorithms must facilitate incremental changes to layout, both local and global. In particular, flexible gate sizing, net buffering and detail placement require a certain amount of unused space in every region of the die. The need for "local" whitespace is further emphasized by temperature and power-density limits. Another requirement, the stability of placement results from run to run, is important to the convergence of physical synthesis loops. Indeed, logic resynthesis targetting local congestion in a given placement or particular critical paths may be irrelevant for another placement produced by the same or a different layout tool.In this work we offer solutions to the above problems. We show how to tie the results of a placer to a previously existing placement, and yet leave room for optimization. In our experiments this technique produces placements with similar congestion maps. We also show how to trade-off wirelength for routability by manipulating whitespace. Empirically, our techniques improve circuit delay of sparse layouts in conjunction with physical synthesis.In the context of earlier proposed techniques for mixed-size placement [2], we tune a state-of-the-art recursive bisection placer to better handle regular netlists that offer a convenient way to represent memories, datapaths and random-logic IP blocks. These modifications and better whitespace distribution improve results on recent mixed-size placement benchmarks.

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Section: Fixed-die Placement In Physical Synthesismentioning

confidence: 99%

On whitespace and stability in mixed-size placement and physical synthesis

Adya

Markov

Villarrubia

2003

ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)

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“…Indeed, in variable-die layout one can always add routing tracks to complete routing at the cost of increased area [20], but this is impossible with a fixed outline.…”

Section: Fixed-die Placement In Physical Synthesismentioning

confidence: 99%

On whitespace and stability in physical synthesis

Adya¹,

Markov

Villarrubia

2006

Integration

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“…It is more suitable for incorporation into constructive placement techniques, such as analytical placers [Parakh et al 1998], quadrisection-based placers [Brenner and Rohe 2003], as well as iterative placement techniques, such as simulated annealing-based placers [Yang et al 2003]. …”

Section: Optimization Techniquesmentioning

confidence: 99%

Large-scale circuit placement

Cong¹,

Shinnerl²,

Xie³

et al. 2005

ACM Trans. Des. Autom. Electron. Syst.

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Placement is one of the most important steps in the RTL-to-GDSII synthesis process, as it directly defines the interconnects, which have become the bottleneck in circuit and system performance in deep submicron technologies. The placement problem has been studied extensively in the past 30 years. However, recent studies show that existing placement solutions are surprisingly far from optimal. The first part of this tutorial summarizes results from recent optimality and scalability studies of existing placement tools. These studies show that the results of leading placement tools from both industry and academia may be up to 50% to 150% away from optimal in total wirelength. If such a gap can be closed, the corresponding performance improvement will be equivalent to several technology-generation advancements. The second part of the tutorial highlights the recent progress on large-scale circuit placement, including techniques for wirelength minimization, routability optimization, and performance optimization.

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Congestion driven quadratic placement

Cited by 17 publications

References 7 publications

On whitespace and stability in mixed-size placement and physical synthesis

On whitespace and stability in mixed-size placement and physical synthesis

On whitespace and stability in physical synthesis

Large-scale circuit placement

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