Constant Coefficient Multiplication Using Look-Up Tables

Wirthlin, Michael

doi:10.1023/b:vlsi.0000008066.95259.b8

Cited by 54 publications

(67 citation statements)

References 11 publications

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“…Each LUT6 generates two bits of P 0 , p 0,i+1 and p 0,i . The next five rows of partial-product bits are grouped and their sum is P 1 , which is a function of A, 2 10 − 2 5 and B [9:5]. The 2 5 possible values of P 1 are pre-computed and generated by a proposed two-operand adder, which adds the generated value to P 0 and produces an accumulated sum, X 1 .…”

Section: Radix-2 Multiplication By a Constantmentioning

confidence: 99%

“…P 0 is a function of the constant A, the constant 2 12 + 2 5 − 2 0 and a 5-bit sub-vector of the variable B, B [4:0]. The 2 5 possible values of P 0 are pre-computed and generated using LUT6s. Each LUT6 generates two bits of P 0 , p 0,i+1 and p 0,i .…”

Section: Radix-2 Multiplication By a Constantmentioning

confidence: 99%

“…Chapman's KCM algorithm uses LUT-based lookup tables to generate radix-16 partial products, specifically targeting Xilinx FPGAs with 4-input LUTs [3,4]. Wirthlin generalizes this approach and presents a method to merge the lookup with addition logic that is also specific to Xilinx FPGAs with 4-input LUTs [5]. Hormigo et al extend Wirthlin's work to include runtime self-reconfiguration [6].…”

Section: Introductionmentioning

confidence: 99%

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Reduced-Area Constant-Coefficient and Multiple-Constant Multipliers for Xilinx FPGAs with 6-Input LUTs

Walters

2017

Electronics

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Multiplication by a constant is a common operation for many signal, image, and video processing applications that are implemented in field-programmable gate arrays (FPGAs). Constant-coefficient multipliers (KCMs) are often implemented in the logic fabric using lookup tables (LUTs), reserving embedded hard multipliers for general-purpose multiplication. This paper describes a two-operand addition circuit from previous work and shows how it can be used to generate and add pre-computed partial products to implement KCMs. A novel method for pre-computing partial products for KCMs with a negative constant is also presented. These KCMs are then extended to have two to eight coefficients that may be selected by a control signal at runtime to implement time-multiplexed multiple-constant multiplication. Synthesis results show that proposed pipelined KCMs use 27.4% fewer LUTs on average and have a median LUT-delay product that is 12% lower than comparable LogiCORE IP KCMs. Proposed pipelined KCMs with two to eight selectable coefficients use 46% to 70% fewer LUTs than the best LogiCORE IP based alternative and most are faster than using a LogiCORE IP multiplier with a coefficient lookup function. They also outperform the state-of-the-art in the literature, using 22% to 57% fewer slices than the smallest pipelined adder graph (PAG) fusion designs and operate 7% to 30% faster than the fastest PAG fusion designs for the same operand size and number of selectable coefficients. For KCMs and KCMs with selectable coefficients of a given operand size, the placement and routing of LUTs remains the same for all positive and negative constant values, which is advantageous for runtime partial reconfiguration.

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Section: Radix-2 Multiplication By a Constantmentioning

confidence: 99%

Section: Radix-2 Multiplication By a Constantmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Reduced-Area Constant-Coefficient and Multiple-Constant Multipliers for Xilinx FPGAs with 6-Input LUTs

Walters

2017

Electronics

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“…For larger precisions, we may use a variation of the KCM technique, due to Chapman [1] and further studied by Wirthlin [2]. The original KCM method addresses the multiplication by an integer constant.…”

Section: B Table-based Constant Multipliers For Fpgasmentioning

confidence: 99%

“…The constant multipliers are built using an evolution of the KCM algorithm [1], [2] that manages multiplications by a real constant [3]. The summation is efficiently performed thanks to the BitHeap framework recently introduced in FloPoCo [4].…”

Section: Introductionmentioning

confidence: 99%

Sum-of-product architectures computing just right

Dinechin

Istoan

Massouri

2014

2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors

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Abstract-Many digital filters and signal-processing transforms can be expressed as a sum of products with constants (SPC). This paper addresses the automatic construction of low-precision, but high accuracy SPC architectures: these architectures are specified as last-bit accurate with respect to a mathematical definition. In other words, they behave as if the computation was performed with infinite accuracy, then rounded only once to the low-precision output format. This eases the task of porting double-precision code (e.g. Matlab) to low-precision hardware or FPGA. The paper further discusses the construction of the most efficient architectures obeying such a specification, introducing several architectural improvements to this purpose. This approach is demonstrated in a generic, open-source architecture generator tool built upon the FloPoCo framework. It is evaluated on Finite Impulse Response filters for the ZigBee protocol.

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Reconfigurable Arithmetic for High-Performance Computing

Dinechin

Pasca

2013

High-Performance Computing Using FPGAs

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Constant Coefficient Multiplication Using Look-Up Tables

Cited by 54 publications

References 11 publications

Reduced-Area Constant-Coefficient and Multiple-Constant Multipliers for Xilinx FPGAs with 6-Input LUTs

Reduced-Area Constant-Coefficient and Multiple-Constant Multipliers for Xilinx FPGAs with 6-Input LUTs

Sum-of-product architectures computing just right

Reconfigurable Arithmetic for High-Performance Computing

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