Constant power reconfigurable computing

Masle, Adrien Le; Chow, Gary C.T.; Luk, Wayne

doi:10.1109/fpt.2011.6132682

Cited by 11 publications

(3 citation statements)

References 14 publications

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“…After placing the source and sink of a power waster, we let the FPGA compilation tool complete the routing. To minimize the number of FPGA logic resources used by the fence, we do not impose any constraints on the signal routes (e.g., we do not force the routes to pass through LUTs or transparent latches at specific locations [27], [30]).…”

Section: A Wire-based Power Wastermentioning

confidence: 99%

Active Wire Fences for Multitenant FPGAs

Glamočanin

Kostic

et al. 2023

2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)

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When spatially shared among multiple tenants, fieldprogrammable gate arrays (FPGAs) are vulnerable to remote power side-channel analysis attacks. Using carefully crafted onchip voltage sensors, adversaries can extract secrets (e.g., encryption keys or the architectural parameters of neural network accelerators) from collocated tenants. A common countermeasure against power side-channel attacks is hiding; in hiding, the goal is to introduce noise and worsen the signal-to-noise ratio visible to the attacker. In a multitenant FPGA setting, hiding countermeasures can be implemented with an active fence placed between tenants. Previous work demonstrated the effectiveness of active fences built using NAND-based ROs. We enhance the state-of-the-art active fence implementation with novel wire-based power wasters, at no increase in resource overhead. Compared to an RO-based fence, our active wire fence makes the side-channel attack considerably more difficult. When using the RO fence to protect an AES-128 cryptographic module, we recovered all the bytes of the secret key with one million sensor traces, on average. In comparison, when using our novel wire fence, more than six million traces (an improvement of at least 6×) were required to recover all the bits of the secret key.

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Section: A Wire-based Power Wastermentioning

confidence: 99%

Active Wire Fences for Multitenant FPGAs

Glamočanin

Kostic

et al. 2023

2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)

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“…Le Masle et al used a network of on-chip RO sensors and a proportional-integral-derivative controller to monitor and maintain an approximately constant core voltage, effectively reducing the SNR [135]. As actuators, they employed long routing wires (equivalent to high capacitive load).…”

Section: Countermeasuresmentioning

confidence: 99%

Electrical-Level Attacks on CPUs, FPGAs, and GPUs: Survey and Implications in the Heterogeneous Era

Mahmoud

Lenders²,

Stojilović

2022

ACM Comput. Surv.

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Given the need for efficient high-performance computing, computer architectures combining central processing units (CPUs), graphics processing units (GPUs), and field-programmable gate arrays (FPGAs) are currently prevalent. However, each of these components suffers from electrical-level security risks. Moving to heterogeneous systems, with the potential of multitenancy, it is essential to understand and investigate how the security vulnerabilities of individual components may affect the system as a whole. In this work, we provide a survey on the electrical-level attacks on CPUs, FPGAs, and GPUs. Additionally, we discuss whether these attacks can extend to heterogeneous systems and highlight open research directions for ensuring the security of heterogeneous computing systems in the future.

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“…A variety of ways can generate excess noise on the chip. Le Masle et al, [LMCL11] use long wires with many buffers along the route, and feed each wire with controlled switching activities to draw currents in the buffers. Güneysu et al, [Gün10] find in dual-ported memories write contentions result in metastability within the storage cells and lead to increased power consumption.…”

Section: Noise Generationmentioning

confidence: 99%

Power Side Channels in Security ICs: Hardware Countermeasures

Zhang,

Vega,

Taylor

2016

Preprint

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Power side-channel attacks are a very effective cryptanalysis technique that can infer secret keys of security ICs by monitoring a chip's power consumption. Since the emergence of practical attacks in the late 90s, they have been a major threat to many cryptographic-equipped devices including smart cards, encrypted FPGA designs, and mobile phones. Designers and manufacturers of cryptographic devices have in response developed various countermeasures for protection. Attacking methods have also evolved to counteract resistant implementations. This paper reviews foundational power analysis attack techniques and examines a variety of hardware design mitigations. The aim is to highlight exposed vulnerabilities in hardware-based countermeasures for future more secure implementations.

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Constant power reconfigurable computing

Cited by 11 publications

References 14 publications

Active Wire Fences for Multitenant FPGAs

Active Wire Fences for Multitenant FPGAs

Electrical-Level Attacks on CPUs, FPGAs, and GPUs: Survey and Implications in the Heterogeneous Era

Power Side Channels in Security ICs: Hardware Countermeasures

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