Constraint-driven bus matrix synthesis for MPSoC

Pasricha, Sudeep; Dutt, Nikil; Ben-Romdhane, Mohamed

doi:10.1145/1118299.1118309

Cited by 29 publications

(13 citation statements)

References 21 publications

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“…Researches on bus matrix have tried to find out optimal bus matrix architectures considering the number of buses and arbitration schemes [3] [4]. However, these works focusing on on-chip communication architectures have paid no attention to low-level details of memory subsystem as considered in this paper.…”

Section: Related Workmentioning

confidence: 99%

Architecture exploration of NAND flash-based multimedia card

Kim

Park

2008

Proceedings of the Conference on Design, Automation and Test in Europe

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Section: Related Workmentioning

confidence: 99%

Architecture exploration of NAND flash-based multimedia card

Kim

Park

2008

Proceedings of the Conference on Design, Automation and Test in Europe

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“…In [38], the authors present an exact approach to crossbar synthesis, where they integrate the NoC architecture parameter setting with the synthesis process. Their design approach is again based on average traffic rates between different cores and does not consider the variations in traffic rates and overlap among streams.…”

Section: Previous Workmentioning

confidence: 99%

An Application-Specific Design Methodology for On-Chip Crossbar Generation

Murali

Benini

Micheli

2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Designing a power-efficient interconnection architecture for MultiProcessor Systems-on-Chips (MPSoCs) satisfying the application performance constraints is a nontrivial task. In order to meet the tight time-to-market constraints and to effectively handle the design complexity, it is essential to provide a computer-aided design tool support for automating this task. In this paper, we address the issue of "application-specific design of optimal crossbar architecture" satisfying the performance requirements of the application and optimal binding of the cores onto the crossbar resources. We present a simulation-based design approach that is based on the analysis of the actual traffic trace of the application, considering local variations in traffic rates, temporal overlap among traffic streams, and criticality of traffic streams. Our approach is physical design aware, where the wiring complexity of the crossbar architecture is also considered during the design process. This leads to detecting timing violations on the wires early in the design cycle and to having accurate estimates of the power consumption on the wires. We apply our methodology onto several MPSoC designs, and the synthesized crossbar platforms are validated for performance by cycle-accurate SystemC simulation of the designs. The crossbar matrix power consumption values are based on the synthesis of the register transfer level models of the designs, obtained using industry standard tools. The experimental case studies show large reduction in communication architecture power consumption (45.3% on average) and total wirelength (38% on average) for the MPSoC designs when compared with traditional design approaches. The synthesized crossbar designs also lead to large reduction in transaction latencies (up to 7×) when compared with the existing design approaches.

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“…Our previous work has shown the effectiveness of TDMA/RR for this purpose [26]. More details on the branch and bound-clustering algorithm can be found in [46].…”

Section: Phase 2 Matrix Map and Analyzementioning

confidence: 99%