Constraint graph analysis of multithreaded programs

Cain, Harold W.; Lipasti, Mikko H.; Nair, Ravi

doi:10.1109/pact.2003.1237997

Cited by 10 publications

(5 citation statements)

References 38 publications

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“…We ignore reflexivity of by not explicitly adding an edge from each node to itself. Using directed graphs to model relations between memory operations for various purposes can also be found in prior work [4,7,15,16,18].…”

Section: Algorithmsmentioning

confidence: 99%

Efficient algorithms for verifying memory consistency

Manovit

Hangal²

2005

Proceedings of the Seventeenth Annual ACM Symposium on Parallelism in Algorithms and Architectures

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One approach in verifying the correctness of a multiprocessor system is to show that its execution results comply with the memory consistency model it is meant to implement. It has been shown in prior work, however, that accurately verifying such compliance even of a single execution result is an NP-complete problem, for an unlimited number of processors. In this paper, we present a suite of post-mortem algorithms that perform the compliance check in an efficient, although not exhaustive, manner. Our algorithms employ the concept of vector clocks together with a heuristic made from a variation of the problem in P class. An implementation of these algorithms has been successful in efficiently detecting several bugs during the course of validating the design of commercial microprocessors and systems.Although our algorithms are presented with the Total Store Order (TSO) memory model, the ideas can also be applied to other models ranging from Sequential Consistency (SC) to a more relaxed one such as Relaxed Memory Order (RMO).

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Section: Algorithmsmentioning

confidence: 99%

Efficient algorithms for verifying memory consistency

Manovit

Hangal²

2005

Proceedings of the Seventeenth Annual ACM Symposium on Parallelism in Algorithms and Architectures

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show abstract

“…The idea of using a constraint graph to model relations between memory operations has been used before in the context of verifying ordering, or analyzing the performance of multithreaded programs [5][11] [16].…”

Section: Related Workmentioning

confidence: 99%

TSOtool: a program for verifying memory systems using the memory consistency model

Hangal¹,

Vahia²,

Manovit³

et al.

Proceedings. 31st Annual International Symposium on Computer Architecture, 2004.

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In this paper, we describe TSOtool, a program to check the behavior of the memory subsystem in a shared memory multiprocessor. TSOtool runs pseudo-randomly generated programs with data races on a system compliant with the Total Store Order (TSO) memory consistency model; it then checks the results of the program against the formal TSO specification. Such analysis can expose subtle memory errors like data corruption, atomicity violation and illegal instruction ordering.While verifying TSO compliance completely is an NPcomplete problem, we describe a new polynomial time algorithm which is incorporated in TSOtool. In spite of being incomplete, it has been successful in detecting several bugs in the design of commercial microprocessors and systems, during both pre-silicon and post-silicon phases of validation.

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“…Partial orders of multi-processor events, constructed from memory accesses and data dependencies, have been used to reason about weakly consistent memory systems [24], [21] and verify their implementations [25], [26], [27], [28]. Our solution uses a similar approach to establish ordering relationships between observed multi-processor events, adapted to the constraints of architectural coverage collection.…”

Section: Related Workmentioning

confidence: 99%

Architectural Trace-Based Functional Coverage for Multiprocessor Verification

Mammo

Larimer

Morgan

et al. 2012

2012 13th International Workshop on Microprocessor Test and Verification (MTV)

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Abstract-Functional coverage plays a pivotal role in assuring the quality of input stimuli used in the verification of modern digital designs. For an out-of-order multi-processor design, simulation of a detailed model of the design is often required to observe relevant design behaviors for functional coverage. However, since such a model is not available during the early phases of test development, verification teams are forced to wait until much later in the verification process to evaluate the quality of their test cases. Even then, the quality of the tests can be assured only on one specific design implementation -an undesirable characteristic for test and regression suites that are meant to be used across multiple generations and/or implementations of an architecture. This work addresses this issue by presenting a novel, implementation-independent, execution tracebased, coverage collection solution. Our solution enables the early evaluation of multi-processor tests using a high-level model of a design. In addition, it can be deployed with detailed design models, if desired, for further analysis alongside implementationspecific coverage models.

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Constraint graph analysis of multithreaded programs

Cited by 10 publications

References 38 publications

Efficient algorithms for verifying memory consistency

Efficient algorithms for verifying memory consistency

TSOtool: a program for verifying memory systems using the memory consistency model

Architectural Trace-Based Functional Coverage for Multiprocessor Verification

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