Constructing large and fast multi-level cell STT-MRAM based cache for embedded processors

Jiang, Lei; Zhao, Bo; Zhang, Youtao; Yang, Jun

doi:10.1145/2228360.2228521

Cited by 61 publications

(22 citation statements)

References 16 publications

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“…We use the binary-search read-out model in our framework [48], and the number of readout steps is determined by the number of stored bits. For example, with two-bit/cell and three-bit/cell MLCs, two-and three-read steps (respectively) are required.…”

Section: Read Operation Modelingmentioning

confidence: 99%

DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability

Mittal

Wang

Vetter

2017

JLPEA

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Abstract:To enable the design of large capacity memory structures, novel memory technologies such as non-volatile memory (NVM) and novel fabrication approaches, e.g., 3D stacking and multi-level cell (MLC) design have been explored. The existing modeling tools, however, cover only a few memory technologies, technology nodes and fabrication approaches. We present DESTINY, a tool for modeling 2D/3D memories designed using SRAM, resistive RAM (ReRAM), spin transfer torque RAM (STT-RAM), phase change RAM (PCM) and embedded DRAM (eDRAM) and 2D memories designed using spin orbit torque RAM (SOT-RAM), domain wall memory (DWM) and Flash memory. In addition to single-level cell (SLC) designs for all of these memories, DESTINY also supports modeling MLC designs for NVMs. We have extensively validated DESTINY against commercial and research prototypes of these memories. DESTINY is very useful for performing design-space exploration across several dimensions, such as optimizing for a target (e.g., latency, area or energy-delay product) for a given memory technology, choosing the suitable memory technology or fabrication method (i.e., 2D v/s 3D) for a given optimization target, etc. We believe that DESTINY will boost studies of next-generation memory architectures used in systems ranging from mobile devices to extreme-scale supercomputers. The latest source-code of DESTINY is available from the following git repository: https://bitbucket.org/sparsh_mittal/destiny_v2.

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Section: Read Operation Modelingmentioning

confidence: 99%

DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability

Mittal

Wang

Vetter

2017

JLPEA

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“…Two different multilevel STT-MRAM structures that have been proposed earlier are depicted in Figure 2 [Ishigaki et al 2010;Lou et al 2008;Jiang et al 2012]. The first structure, shown in Figure 2(a) [Ishigaki et al 2010], consists of two MTJ stacks connected in series.…”

Section: Multilevel Stt-mrammentioning

confidence: 99%

“…This structure provides four different resistance levels for reading out the two bit information. The second multilevel STT-MRAM structure, shown in Figure 2(b), employs a free layer that is partitioned into two domains [Lou et al 2008;Jiang et al 2012]. The domain with larger area requires a larger current density to switch and is termed as 'hard' domain.…”

Section: Multilevel Stt-mrammentioning

confidence: 99%

Energy-Efficient All-Spin Cache Hierarchy Using Shift-Based Writes and Multilevel Storage

Venkatesan

Sharad

Roy

et al. 2015

J. Emerg. Technol. Comput. Syst.

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Spintronic memories are considered to be promising candidates for future on-chip memories due to their high density, nonvolatility, and near-zero leakage. However, they also face challenges such as high write energy and latency and limited read speed due to single-ended sensing. Further, the conflicting requirements of read and write operations lead to stringent design constraints that severely compromises their benefits.Recently, domain wall memory was proposed as a spintronic memory that has a potential for very high density by storing multiple bits in the domains of a ferromagnetic nanowire. While reliable operation of DWM memory with multiple domains faces many challenges, single-bit cells that utilize domain wall motion for writes have been experimentally demonstrated [Fukami et al. 2009]. This bit-cell, which we refer to as Domain Wall Memory with Shift-based Write (DWM-SW), achieves improved write efficiency and features decoupled read-write paths, enabling independent optimizations of read and write operations. However, these benefits are achieved at the cost of sacrificing the original goal of improved density. In this work, we explore multilevel storage as a new direction to enhance the density benefits of DWM-SW. At the device level, we propose a new device-multilevel DWM with shift-based write (ML-DWM-SW)-that is capable of storing 2 bits in a single device. At the circuit level, we propose a ML-DWM-SW based bit-cell design and layout. The ML-DWM-SW bit-cell incurs no additional area overhead compared to the DWM-SW bit-cell despite storing an additional bit, thereby achieving roughly twice the density. However, it requires a two-step write operation and has data-dependent read and write energies, which pose unique challenges. To address these issues, we propose suitable architectural optimizations: (i) intra-word interleaving and (ii) bit encoding. We design "all-spin" cache architectures using the proposed ML-DWM-SW bit-cell for both general purpose processors as well as general purpose graphics processing units (GPGPUs). We perform an iso-capacity replacement of SRAM with spintronic memories and study the energy and area benefits at iso-performance conditions. For general purpose processors, the ML-DWM-SW cache achieves 10X reduction in energy and 4.4X reduction in cache area compared to an SRAM cache and 2X and 1.7X reduction in energy and area, respectively, compared to an STT-MRAM cache. For GPGPUs, the ML-DWM-SW cache achieves 5.3X reduction in energy and 3.6X area reduction compared to SRAM and 3.5X energy reduction and 1.9X area reduction compared to STT-MRAM. . 2015. Energy-efficient all-spin cache hierarchy using shift-based writes and multilevel storage. ACM

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“…Several projects [18][19] [24][34] focus on improving the MLC NVM write performance/energy/endurance by improving the NVM infrastructure and memory controller. Jiang et al [17] also worked on improving the performance of a multilevel STT-RAM. Saadeldeen et al [27] use memristors for branch prediction.…”

Section: Multi-level Non-volatile Memorymentioning

confidence: 99%

SpongeDirectory

Zhang

Strukov

Saadeldeen

et al. 2014

Proceedings of the 23rd International Conference on Parallel Architectures and Compilation

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Cache-coherent shared memory is critical for programmability in many-core systems. Several directory-based schemes have been proposed, but dynamic, non-uniform sharing make efficient directory storage challenging, with each giving up storage space, performance or energy.We introduce SpongeDirectory, a sparse directory structure that exploits multi-level memristory technology. SpongeDirectory expands directory storage in-place when needed by increasing the number of bits stored on a single memristor device, trading latency and energy for storage.We explore several SpongeDirectory configurations, finding that a provisioning rate of 0.5x with memristors optimized for low energy consumption is the most competitive. This optimal SpongeDirectory configuration has performance comparable to a conventional sparse directory, requires 18× less storage space, and consumes 8× less energy.

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Constructing large and fast multi-level cell STT-MRAM based cache for embedded processors

Cited by 61 publications

References 16 publications

DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability

DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability

Energy-Efficient All-Spin Cache Hierarchy Using Shift-Based Writes and Multilevel Storage

SpongeDirectory

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