Contact hole shrink process using directed self-assembly

Seino, Yuriko; Yonemitsu, Hiroki; Sato, Hiroki; Kanno, Manabu; Kato, Hikazu; Kobayashi, Katsutoshi; Kawanishi, Ayako; Azuma, Tsukasa; Muramatsu, Makoto; Nagahara, Seiji; Kitano, Takahiro; Toshima, Takayuki

doi:10.1117/12.915652

Cited by 20 publications

(21 citation statements)

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“…Then the wafer was developed by organic solvent for 30 s. Figure 2 shows top-down and cross-sectional SEM images after wet development. The dose condition in this study was chosen as 1800 mJ∕cm 2 .…”

Section: Process Window Of Dsalmentioning

confidence: 99%

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Contact hole shrink process using graphoepitaxial directed self-assembly lithography

Seino

Yonemitsu

Sato

et al. 2013

J. Micro/Nanolith. MEMS MOEMS

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Abstract. A contact hole shrink process using directed self-assembly lithography (DSAL) for sub-30 nm contact hole patterning is reported on. DSAL using graphoepitaxy and poly (styrene-block-methyl methacrylate) (PS-b-PMMA) a block copolymer (BCP) was demonstrated and characteristics of our process are spin-on-carbon prepattern and wet development. Feasibility of DSAL for semiconductor device manufacturing was investigated in terms of DSAL process window. Wet development process was optimized first; then critical dimension (CD) tolerance of prepattern was evaluated from three different aspects, which are DSA hole CD, contact edge roughness (CER), and hole open yield. Within 70 þ ∕ − 5 nm hole prepattern CD, 99.3% hole open yield was obtained and CD tolerance was 10 nm. Matching between polymer size and prepattern size is critical, because thick PS residual layer appears at the hole bottom when the prepattern holes are too small or too large and results in missing holes after pattern transfer. We verified the DSAL process on a 300-mm wafer at target prepattern CD and succeeded in patterning sub-30 nm holes on center, middle, and edge of wafer. Average prepattern CD of 72 nm could be shrunk uniformly to DSA hole pattern of 28.5 nm. By the DSAL process, CD uniformity was greatly improved from 7.6 to 1.4 nm, and CER was also improved from 3.9 to 0.73 nm. Those values represent typical DSAL rectification characteristics and are significant for semiconductor manufacturing. It is clearly demonstrated that the contact hole shrink using DSAL is a promising patterning method for next-generation lithography.

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Section: Process Window Of Dsalmentioning

confidence: 99%

“…1,2 The wet development process provides selective removal of PMMA block. It also provides more remaining of PS film, which works as a mask on pattern transfer by reactive ion etching (RIE).…”

Section: Introductionmentioning

confidence: 99%

Contact hole shrink process using graphoepitaxial directed self-assembly lithography

Seino

Yonemitsu

Sato

et al. 2013

J. Micro/Nanolith. MEMS MOEMS

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“…The target CD was 70 nm in diameter. According to our previous study [4], hole open yield was 100% with the hole CD between 65 nm and 75 nm, although the sample size was as small as 45 holes/chip. The SOC pattern was used as a pre-pattern of graphoepitaxy.…”

Section: Fabrication Processmentioning

confidence: 82%

Electrical Via Chain Yield for DSA Contact Hole Shrink Process

Katō

Seino

Yonemitsu

et al. 2013

J. Photopol. Sci. Technol.

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In this study, we conducted electrical via chain yield tests for the purpose of verifying the total process performance of directed self-assembly (DSA) contact hole shrink process. DSA was utilized on the via level connecting between two metal levels. From the analysis of single via resistance data, the best process condition was determined and the via chain yield was obtained. The best yield was 74% at the via chain size of 2.3k and one chip passed the test at the via chain size of 358k. In order to find the root cause of the via chain yield degradation, the failure location was identified by absorbed electron current images and STEM images were taken. It was found that the via did not contact the lower metal level at the failure location. However, we concluded that it was not necessarily caused by DSA process because such failure mode was also observed for the via chains without DSA. Although the via chain size tested at the pre-production stage is much larger by orders of magnitude than the via chain size tested in this study, we believe that significant progress has been made in this study toward semiconductor device manufacturing using DSA contact hole shrink process.

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“…The use of wet development enables more PS and resist pre-pattern thickness to be available as a etch mask into the underlying substrate. More detailed descriptions of the wet development process are published in a companion paper within SPIE 2012 as well as in previous publications [13,14]. The organic to organic etch selectivity between PS and PMMA is of high interest due to the need to have enough PS remaining to enable etch transfer into the substrate.…”

Section: Pattern Transfer Using Wet or Dry (Etch) Developmentmentioning

confidence: 99%

Pattern scaling with directed self assembly through lithography and etch process integration

Rathsack

Somervell

Hooge

et al. 2012

Alternative Lithographic Technologies IV

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Directed self-assembly (DSA) has the potential to extend scaling for both line/space and hole patterns. DSA has shown the capability for pitch reduction (multiplication), hole shrinks, CD self-healing as well as a pathway towards line edge roughness (LER) and pattern collapse improvement [1][2][3][4]. The current challenges for industry adoption are materials maturity, practical process integration, hardware capability, defect reduction and design integration. Tokyo Electron (TEL) has created close collaborations with customers, consortia and material suppliers to address these challenges with the long term goal of robust manufacturability.This paper provides a wide range of DSA demonstrations to accommodate different device applications. In collaboration with IMEC, directed line/space patterns at 12.5 and 14 nm HP are demonstrated with PS-b-PMMA (poly(styrene-b-methylmethacrylate)) using both chemo and grapho-epitaxy process flows. Pre-pattern exposure latitudes of >25% (max) have been demonstrated with 4X directed self-assembly on 300 mm wafers for both the lift off and etch guide chemo-epitaxy process flows. Within TEL's Technology Development Center (TDC), directed selfassembly processes have been applied to holes for both CD shrink and variation reduction. Using a PS-b-PMMA hole shrink process, negative tone developed pre-pattern holes are reduced to below 30 nm with critical dimension uniformity (CDU) of 0.9 nm (3σ) and contact edge roughness (CER) of 0.8 nm (3σ). To generate higher resolution beyond a PS-b-PMMA system, a high chi (χ) material is used to demonstrate 9 nm HP line/ space post-etch patterns. In this paper, TEL presents process solutions for both line/space and hole DSA process integrations.

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Contact hole shrink process using directed self-assembly

Cited by 20 publications

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Contact hole shrink process using graphoepitaxial directed self-assembly lithography

Contact hole shrink process using graphoepitaxial directed self-assembly lithography

Electrical Via Chain Yield for DSA Contact Hole Shrink Process

Pattern scaling with directed self assembly through lithography and etch process integration

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