Contact hole shrink process using graphoepitaxial directed self-assembly lithography

Abstract

Abstract. A contact hole shrink process using directed self-assembly lithography (DSAL) for sub-30 nm contact hole patterning is reported on. DSAL using graphoepitaxy and poly (styrene-block-methyl methacrylate) (PS-b-PMMA) a block copolymer (BCP) was demonstrated and characteristics of our process are spin-on-carbon prepattern and wet development. Feasibility of DSAL for semiconductor device manufacturing was investigated in terms of DSAL process window. Wet development process was optimized first; then critical dimension (CD) tolerance of prepattern was evaluated from three different aspects, which are DSA hole CD, contact edge roughness (CER), and hole open yield. Within 70 þ ∕ − 5 nm hole prepattern CD, 99.3% hole open yield was obtained and CD tolerance was 10 nm. Matching between polymer size and prepattern size is critical, because thick PS residual layer appears at the hole bottom when the prepattern holes are too small or too large and results in missing holes after pattern transfer. We verified the DSAL process on a 300-mm wafer at target prepattern CD and succeeded in patterning sub-30 nm holes on center, middle, and edge of wafer. Average prepattern CD of 72 nm could be shrunk uniformly to DSA hole pattern of 28.5 nm. By the DSAL process, CD uniformity was greatly improved from 7.6 to 1.4 nm, and CER was also improved from 3.9 to 0.73 nm. Those values represent typical DSAL rectification characteristics and are significant for semiconductor manufacturing. It is clearly demonstrated that the contact hole shrink using DSAL is a promising patterning method for next-generation lithography.

Optimization of directed self-assembly hole shrink process with simplified model

“…2,4 As shown in Fig. 1(d), the relatively thick PS layer remains between the cylindrical PMMA domain and the bottom surface.…”

“…Some DSA patterning processes have already been investigated in a manufacturing environment, e.g., density multiplication of line (or hole) patterns, 1 and hole shrink process. 2 One of the remaining issues for these DSA processes is to reduce the defect level. 3,4 According to the International Technology Roadmap for Semiconductors (ITRS), the defect level for the current DSA processes is still far from the manufacturing requirement.…”

“…Note that the sidewalls and bottom surface of the guide hole are covered with a very thin layer of PMMA due to their higher affinity to the PMMA. 2,6 The diameter of the cylindrical PMMA domain is typically on the order of ∼20 to 30 nm, depending on the molecular weight of the PS-b-PMMA. After the selective removal of the cylindrical PMMA domain, the smaller hole is generated in the guide hole pattern.…”

“…1). 2 First, the guide holes (e.g., contact or via holes) are etched into the silicon-on-glass (SOG) and silicon-on-carbon (SOC) hardmasks, using conventional lithographic methods [ Fig. 1(a)].…”

A Simulation Study on Defectivity in Directed Self-assembly Lithography

“…Many applications such as hole shrink [1][2][3][4][5] and line/space (L/S) patterning for FinFET device [6] have been reported in recent years. In the L/S applications, some prospective process flows such as the lift-off process [7], the LiNe process [8], the SMART TM process [9], and the coordinated line epitaxy (COOL) process [10][11][12][13][14] have been demonstrated in full-wafer experiments.…”