Contending memory in heterogeneous SoCs: Evolution in NVIDIA Tegra embedded platforms

Abstract

Modern embedded platforms are known to be constrained by size, weight and power (SWaP) requirements. In such contexts, achieving the desired performance-per-watt target calls for increasing the number of processors rather than ramping up their voltage and frequency. Hence, generation after generation, modern heterogeneous System on Chips (SoC) present a higher number of cores within their CPU complexes as well as a wider variety of accelerators that leverages massively parallel compute architectures. Previous literature demonstrated that while increasing parallelism is theoretically optimal for improving on average performance, shared memory hierarchies (i.e. caches and system DRAM) act as a bottleneck by exposing the platform processors to severe contention on memory accesses, hence dramatically impacting performance and timing predictability. In this work we characterize how subsequent generations of embedded platforms from the NVIDIA Tegra family balanced the increasing parallelism of each platform's processors with the consequent higher potential on memory interference. We also present an open-source software for generating test scenarios aimed at measuring memory contention in highly heterogeneous SoCs.

Machine Learning Techniques for Understanding and Predicting Memory Interference in CPU-GPU Embedded Systems

“…Interference on shared memory resources has been previously observed in both multicore CPUs [10]- [13], within the GPU computing clusters [14], [15] and between CPU and GPU in integrated SoCs [1], [3], [16]. Focusing on this latter topic, several approaches have been proposed in order to mitigate the effect of memory interference on both performance and predictability.…”

“…In order to generate variable CPU-side memory interference, an open-source software designed for heterogeneous SoCs has been set up, HeSoC-mark [16] 2 (details in Section IV-B). The Nvidia board under test is configured for maximum performance (MAXN).…”

Understanding and Mitigating Memory Interference in FPGA-based HeSoCs

“…Memory interference has been extensively studied in the context of multi-core CPU and GP-GPU HeSoCs [2] [11] but only very few papers have addressed the problem in FPGA-based HeSoCs. A. Bansal et al [1] characterize the memory subsystem of the ZU9EG MPSoC, through micro-benchmarks.…”

“…To conduct an in-depth analysis and characterization of the memory interference in a SoC a typical methodology is that of relying on synthetic workloads aimed at stressing corner cases [2], [9]. When focusing on a FPGA-based HeSoC, a typical way of generating configurable synthetic memory traffic is that of deploying some form of traffic generators [3].…”

“…Most papers studying this problem target multi-core CPUs [1], [10] or GPU-based HeSoCs [2], [6], [11], while not much has been done so far in the context of FPGAbased HeSoCs. This paper aims at filling this gap by means of: i) extensive memory interference characterization on two state-of-the-art FPGA-based HeSoCs for high-end embedded systems: the Xilinx Zynq UltraScale+ ZU9EG and the Xilinx Versal VC1902 ACAP; ii) an implementation of the CMRI technique [9] suitable for generic FPGA accelerators; iii) a thorough assessment of the resulting benefits on the memory bandwidth exploitation.…”