No abstract

This paper presents SPHERE, a project aimed at the realization of an integrated framework to abstract the hardware complexity of interconnected, modern system-on-chips (SoC) and simplify the management of their heterogeneous computational resources. The SPHERE framework leverages hypervisor technology to virtualize computational resources and isolate the behavior of different subsystems running on the same platform, while providing safety, security, and real-time communication mechanisms. The main challenges addressed by SPHERE are discussed in the paper along with a set of new technologies developed in the context of the project. They include isolation mechanisms for mixed-criticality applications, predictable I/O virtualization, the management of time-sensitive networks with heterogeneous traffic flows, and the management of field-programmable gate arrays (FPGA) to provide efficient implementations for cryptography modules, as well as hardware acceleration for deep neural networks. The SPHERE architecture is validated through an autonomous driving use-case.INDEX TERMS cyber-physical systems, embedded systems, real-time systems, hypervisor, FPGA.

The advent of commercial-of-the-shelf (COTS) heterogeneous\ud many-core platforms is opening up a series of opportunities\ud in the embedded computing market. Integrating multiple\ud computing elements running at smaller frequencies allows obtaining\ud impressive performance capabilities at a reduced power\ud consumption. These platforms can be successfully adopted to\ud build the next-generation of self-driving vehicles, where Advanced\ud Driver Assistance Systems (ADAS) need to process unprecedently\ud higher computing workloads at low power budgets. Unfortunately,\ud the current methodologies for providing real-time guarantees\ud are uneffective when applied to the complex architectures\ud of modern many-cores. Having impressive average performances\ud with no guaranteed bounds on the response times of the critical\ud computing activities is of little if no use to these applications.\ud Project HERCULES will provide the required technological\ud infrastructure to obtain an order-of-magnitude improvement in\ud the cost and power consumption of next generation automotive\ud systems. This paper presents the integrated software framework\ud of the project, which allows achieving predictable performance\ud on top of cutting-edge heterogeneous COTS platforms. The\ud proposed software stack will let both real-time and non real-time\ud application coexist on next-generation, power-efficient embedded\ud platform, with preserved timing guarantees

The current trend in designing Advanced Driving Assistance System (ADAS) is to enhance their computing power by using modern multi/many core accelerators. For many critical applications such as pedestrian detection, line following, and path planning the Graphic Processing Unit (GPU) is the most popular choice for obtaining orders of magnitude increases in performance at modest power consumption. This is made possible by exploiting the general purpose nature of today's GPUs, as such devices are known to express unprecedented performance per watt on generic embarrassingly parallel workloads (as opposed of just graphical rendering, as GPUs where only designed to sustain in previous generations). In this work, we explore novel challenges that system engineers have to face in terms of realtime constraints and functional safety when the GPU is the chosen accelerator. More specifically, we investigate how much of the adopted safety standards currently applied for traditional platforms can be translated to a GPU accelerated platform used in critical scenarios.

Modern embedded platforms are known to be constrained by size, weight and power (SWaP) requirements. In such contexts, achieving the desired performance-per-watt target calls for increasing the number of processors rather than ramping up their voltage and frequency. Hence, generation after generation, modern heterogeneous System on Chips (SoC) present a higher number of cores within their CPU complexes as well as a wider variety of accelerators that leverages massively parallel compute architectures. Previous literature demonstrated that while increasing parallelism is theoretically optimal for improving on average performance, shared memory hierarchies (i.e. caches and system DRAM) act as a bottleneck by exposing the platform processors to severe contention on memory accesses, hence dramatically impacting performance and timing predictability. In this work we characterize how subsequent generations of embedded platforms from the NVIDIA Tegra family balanced the increasing parallelism of each platform's processors with the consequent higher potential on memory interference. We also present an open-source software for generating test scenarios aimed at measuring memory contention in highly heterogeneous SoCs.