Contention-Free Interleavers for High-Throughput Turbo Decoding

Nimbalker, Ajit; Blankenship, T.K.; Classon, B.; Fuja, T.E.; Costello, Daniel J.

doi:10.1109/tcomm.2008.050502

Cited by 37 publications

(45 citation statements)

References 23 publications

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“…The number of symbols in each set is fixed for a given interleaver. Block interleaver may have good minimum distance, but the high multiplicity of low weight codewords makes this interleaver as unsuitable [2].…”

Section: Block Interleavermentioning

confidence: 99%

Ber Analysis of Turbo Code Interleaver

Bahirgonde¹,

Dixit²

2015

IJCA

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This paper presents a low complexity interleaver design that facilitates high throughput Turbo decoding required for next generation wireless systems. When a parallel decoder structure is considered, interleaver design is the most important issue. In such parallel decoder, the contention problem occurs when more than one extrinsic value references to the same memory block for read or write purpose. This paper focuses on the alternate method for QPP interleaver which shows improved BER performance for large frame size. Bit reversed indexing is used to generate interleaved addresses. A counter is used to generate sequential address as well as interleaved address. The number of address lines of memory which stores data , depends upon frame size of data. In this paper, a comparison is made between best proved interleaver and proposed interleaver on the basis of BER performance for different number of iterations, different frame size and different decoding algorithms. General TermsInterleaver, Turbo Decoder, Bit reverse indexing.

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Section: Block Interleavermentioning

confidence: 99%

Ber Analysis of Turbo Code Interleaver

Bahirgonde¹,

Dixit²

2015

IJCA

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“…In this paper, we use the parallel decoding and the parallel conflict-free interleaver, so that decoding delay are greater saved. To solve the problem of memory conflicts which generated by Turbo codes when they are parallel decoding, the conception of non-conflict interleaver is introduced [14], in which interleaver and anti-interleaver functions are required to meet the conditions :…”

Section: Parallel Efficient Turbo Decoding Of Conflict-free Interleavermentioning

confidence: 99%

Joint Encryption and Error Correction Technical Research Applied an Efficient Turbo Code

Yao¹,

Liu²,

Yang³

2015

IJSIA

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“…In general, a Turbo interleaver/de-interleaver f(x), is said to be contention-free for a window size of L if and only if it satisfies the following constraint [10,28,29] …”

Section: Qpp Contention-free Propertymentioning

confidence: 99%

Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder

Sun

Cavallaro

2011

Integration

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a b s t r a c tWe present an efficient VLSI architecture for 3GPP LTE/LTE-Advance Turbo decoder by utilizing the algebraic-geometric properties of the quadratic permutation polynomial (QPP) interleaver. The highthroughput 3GPP LTE/LTE-Advance Turbo codes require a highly-parallel decoder architecture. Turbo interleaver is known to be the main obstacle to the decoder parallelism due to the collisions it introduces in accesses to memory. The QPP interleaver solves the memory contention issues when several MAP decoders are used in parallel to improve Turbo decoding throughput. In this paper, we propose a low-complexity QPP interleaving address generator and a multi-bank memory architecture to enable parallel Turbo decoding. Design trade-offs in terms of area and throughput efficiency are explored to find the optimal architecture. The proposed parallel Turbo decoder has been synthesized, placed and routed in a 65-nm CMOS technology with a core area of 8.3 mm 2 and a maximum clock frequency of 400 MHz. This parallel decoder, comprising 64 MAP decoder cores, can achieve a maximum decoding throughput of 1.28 Gbps at 6 iterations &

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Contention-Free Interleavers for High-Throughput Turbo Decoding

Cited by 37 publications

References 23 publications

Ber Analysis of Turbo Code Interleaver

Ber Analysis of Turbo Code Interleaver

Joint Encryption and Error Correction Technical Research Applied an Efficient Turbo Code

Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder

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