Contention‐tolerant crossbar packet switches

Qu, Guannan; Chang, Hyung Jae; Wang, Jianping; Fang, Zhiyi; Zheng, S. Q.

doi:10.1002/dac.1147

Cited by 11 publications

(8 citation statements)

References 27 publications

(14 reference statements)

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“…In [10], we also developed a mathematic model of CTC(N) using queueing theory and analyzed the existing issues of the CTC architecture: 1. Without internal speedup, the saturated throughput, i.e.…”

Section: Related Workmentioning

confidence: 99%

“…In order to increase the performance, we discussed several improved architectures [10], [12]- [14]. In [10], [12], we proved that 100% throughput achieves with two planes of CTC(N) or with speedup two.…”

Section: Related Workmentioning

confidence: 99%

“…Recently, we propose an innovate switch architecture called Contention-Tolerant Crossbar Switches (CTC(N)) [10]. CTC(N) is able to tolerate output conflict automatically, thus the schedulers are fully distributed over inputs, avoiding central control or signal exchange.…”

Section: Introductionmentioning

confidence: 99%

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Implementing High Throughput Contention-Tolerant Crossbar Switch

Fang

et al. 2015

jcm

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Recently, an innovate switch architecture named Contention-Tolerant Crossbar switch, CTC(N), was proposed. Without resolving output contentions, the controllers are able to fully distributed in CTC(N). It largely reduces the scheduling complexity. However, It has been proved that the saturated switch throughput is bounded by 63% without any scheduling algorithms. In this paper, we present an implementation scheme named Two-Stage Contention-Tolerant Crossbar, denoted as TCTC(N, k). TCTC(N, k) uses Contention-Tolerant Crossbar as its basic switch component. And we will theoretically prove that TCTC(N, k) achieves high throughput with small size CTC components and without complex hardware and internal speedup.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

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Implementing High Throughput Contention-Tolerant Crossbar Switch

Fang

et al. 2015

jcm

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“…Unlike conventional memories in which concurrent multiple writes and/or reads are considered as a speedup, the new buffer architecture presented in [31] can accommodate concurrent multiple writes and one read using memory interleaving techniques without memory speedup. This memory architecture is also used in C T C.N / architecture proposed in [32]. This memory architecture is also used in C T C.N / architecture proposed in [32].…”

Section: Architecturementioning

confidence: 99%

“…Such a buffer consists of multiple memory modules that behave as a single memory with FIFO scheduling policy in such a way that operations by memory accesses are performed concurrently on different modules in the same time slot. This memory architecture is also used in C T C.N / architecture proposed in [32].…”

Section: Architecturementioning

confidence: 99%

A high‐performance switch architecture based on mesh of trees

Chang

Zheng

2012

Int J Communication

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With emergence of various new Internet-enabled devices, such as tablet PCs or smart phones along with their own applications, the traffic growth rate is getting faster and faster these days and demands more communication bandwidth at even faster rate than before. To accommodate this ever-increasing network traffic, even faster Internet routers are required. To respond for these needs, we propose a new mesh of trees based switch architecture, called MOT S.N / switch. In addition, we also propose two more variations of MOT S.N / to further improve it. MOT S.N / is inspired by crossbar with crosspoint buffers. It forms a binary tree for each output line, where each gridpoint buffer ‡ is a leaf node and each internal node is 2-in 1-out merge buffer § emulating FIFO queues. Because of this FIFO characteristic of internal buffers, MOT S.N / ensures QoS like FIFO output-queued switch. The root node of the tree for each output line is the only component connected to the output port where each cell is transmitted to output port without any contention. To limit the number of buffers in MOT S.N / switch, we present one of its improved (practical) variations, IMOTS.N / switch, as well. For IMOTS.N / switch architecture, sizes of the buffers in the fabric are limited by a certain amount. As a downside of IMOTS.N /, however, every cell should go through log 2 N C 1 number of buffers in the fabric to be transmitted to the designated output line. Therefore, for even further improvement, IMOTS.N / with cut-through, denoted as IMOTS-C T .N /, is also proposed in this paper. In IMOTS-C T .N / switch, the cells can cut through one or more empty buffers to be transferred from inputs to outputs with simple 1 or 2 bit signal exchanges between buffers. We analyze the throughput of MOT S.N /, IMOTS.N /, and IMOTS-C T .N / switches and show that they can achieve 100% throughput under Bernoulli independent and identically distributed uniform traffic. Our quantitative simulation results validate the theoretical analysis. ‡ Because the fabric of MOT S.N / switch is not pure crossbar, we call the buffers in the same location in pure crossbar gridpoint buffers. Details will be presented in the following sections. § 2-in 1-out merge buffer can accommodate two memory writes and one memory read simultaneously by using its modularized architecture [31].According to the location of buffers, various crossbar switch architectures have been proposed and studied. The examples of unbuffered crossbar switches are input-queued (IQ), output-queued (OQ), and combined input-queued and output-queued (CIOQ) switches. In OQ switch, cell are forwarded to and queued at output ports without any intermediate delay. As a result, it is very powerful to provide QoS. However, large-sized OQ switch is practically infeasible and remains in theory because the memory speed should be N times faster than the line rate, where N is the size of the switch.In IQ switch, packets are queued at input ports first as they arrive to the switch. For this switch architecture, memory spe...

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Performance of fiber delay‐line buffers in asynchronous packet‐based optical switching networks with wavelength conversion

Zhang

Wang

2014

Int J Communication

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SUMMARYA major challenge in asynchronous packet-based optical networks is packet contention, which occurs when two or more packets head to the same output at the same time. To resolve contention in the optical domain, two primary approaches are wavelength conversion and fiber delay line (FDL) buffering. In wavelength conversion, a contending packet can be converted from one wavelength to another in order to avoid conflict. In FDL buffering, contending packets can be delayed for a fixed amount of time. While the performance of wavelength conversion and FDL buffering has been evaluated extensively in synchronous networks with fixed-sized packets, in this paper, we study the performance of FDL buffers in asynchronous packet-based optical networks with wavelength conversion. An analytical model is proposed to evaluate the performance in terms of packet loss probability and average delay. Extensive simulation and analytical results show that, with appropriate settings, FDL buffers can perform much better in switches with wavelength conversion than in switches with no conversion.

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Contention‐tolerant crossbar packet switches

Cited by 11 publications

References 27 publications

Implementing High Throughput Contention-Tolerant Crossbar Switch

Implementing High Throughput Contention-Tolerant Crossbar Switch

A high‐performance switch architecture based on mesh of trees

Performance of fiber delay‐line buffers in asynchronous packet‐based optical switching networks with wavelength conversion

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