Context Management Scheme Optimization of Coarse-Grained Reconfigurable Architecture for Multimedia Applications

Cao, Peng; Liu, Bo; Yang, Jinjiang; Yang, Jun; Zhang, Meng; Shi, Longxing

doi:10.1109/tvlsi.2017.2695493

Cited by 6 publications

(3 citation statements)

References 23 publications

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“…We compare DNestMap with existing approaches: (1) CacheIn-ner1: Most CGRA compilers [7,11,12] target the innermost loops. More recent works [4,13,16] have used the CMEM as a cache to store the configuration context of recent innermost loops. This baseline evaluates the performance when the innermost loops are dynamically cached in the CMEM using perfect LRU policy.…”

Section: Discussionmentioning

confidence: 99%

“…This is due to their highly constrained power budget -about 40% of the CGRA power is consumed by the on-chip CMEM in [12]. To solve this CMEM capacity constraint, recent works [4,13,16] propose architectural improvements to use the CMEM as a cache that stores the most recently accessed loop-nests at runtime. The dynamic caching leads to performance improvement because more segments of the application can be accelerated and the data transfer between the host and the CGRA is minimized.…”

Section: Introductionmentioning

confidence: 99%

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DNestMap: Mapping Deeply-Nested Loops on Ultra-Low Power CGRAs

Karunaratne¹,

Tan²,

Kulkarni³

et al. 2018

2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

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Coarse-Grained Reconfigurable Arrays (CGRAs) provide high performance, energy-efficient execution of the innermost loops of an application. Most real-world applications, however, comprise of deeply-nested loops with complex and often irregular control flow structures that cannot be mapped to CGRAs by existing compilers. This leads to excessive data transfer costs as the execution continuously alternates between the outer loop-nests on the host processor and the innermost loop on the CGRA accelerator. Moreover, ultralow power CGRAs can only include limited on-chip memory to cache the configuration bitstreams and need frequent swapping of configurations in the presence of multiple innermost loops. We introduce DNestMap, a partitioning and mapping tool for CGRAs, that can judiciously extract the most beneficial code segments of multiple deeply-nested loops and effectively cache them together statically in the configuration memory through spatio-temporal partitioning. DNestMap achieves 1.58X performance improvement compared to dynamic caching of configuration contexts of the innermost loops in the CGRAs with limited on-chip memory. PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE

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Section: Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

DNestMap: Mapping Deeply-Nested Loops on Ultra-Low Power CGRAs

Karunaratne¹,

Tan²,

Kulkarni³

et al. 2018

2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

View full text Add to dashboard Cite

show abstract

“…Ref. [51] proposed a context replacement algorithm based on context frequency weight factor for the hierarchical context cache. It can improve the configuration performance by 13.6%-20.5%.…”

Section: Memory Access Efficiencymentioning

confidence: 99%