Control development for mechatronic systems with a fully reconfigurable pipeline architecture

Rettberg, Achim; Zanella, M.; Lehmann, T.; Dierkes, U.; Rustemeier, C.

doi:10.1109/sbcci.2003.1232834

Cited by 4 publications

(1 citation statement)

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“…The developed approach is applicable to different target architectures. Especially, self-controlled architectures like the one presented in [12] are addressed. A self-controlled architecture has no global control unit; only distributed small control parts are present in the design.…”

Section: Related Workmentioning

confidence: 99%

Integration of Energy Reduction into High-Level Synthesis by Partitioning

Rettberg

Rammig

From Model-Driven Design to Resource Management for Distributed Embedded Systems

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The optimization of power consumption at a very high design level is a critical step towards a power-efficient digital system design. The increasing usage of battery-powered and often wireless portable systems is driving the demand for IC and SoC devices consuming the smallest possible amount of energy. The aim of the method presented in this paper is to integrate low power methods within the scheduling process of the High-Level Synthesis by defining partitions. Starting from an ControUed-Data-Flow-Graph (CDFG) the proposed method uses standard scheduling techniques and path analysis on the graph to identify regions that can be combined to partitions. Each partition has a controlled activation or deactivation mechanism. That means, the partition can be switched off when it is not used. As an example design, a part of the MPEG-2 algorithm is used.

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Section: Related Workmentioning

confidence: 99%