Control of nanogap junction resistance by imposed pulse voltage

Masuda, Yuichiro; Takahashi, Tsuyoshi; Furuta, Shigeo; Ono, Masashi; Shimizu, Tetsuo; Naitoh, Yasuhisa

doi:10.1016/j.apsusc.2009.05.128

Cited by 19 publications

(24 citation statements)

References 9 publications

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“…The switching characteristic strongly relies on the electrode material, the nanogap size, and the crystallinity 12 13 16 17 . The typical switching speed and retention time of NGS at room temperature (293–297 K) are shorter than 1 μs and longer than several years, respectively 12 18 . In general, NGS at high temperatures requires a material with a high melting temperature, although there is a trade-off with the switching voltage 16 .…”

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confidence: 99%

Highly stable, extremely high-temperature, nonvolatile memory based on resistance switching in polycrystalline Pt nanogaps

Suga

Suzuki

Shinomura

et al. 2016

Sci Rep

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Highly stable, nonvolatile, high-temperature memory based on resistance switching was realized using a polycrystalline platinum (Pt) nanogap. The operating temperature of the memory can be drastically increased by the presence of a sharp-edged Pt crystal facet in the nanogap. A short distance between the facet edges maintains the nanogap shape at high temperature, and the sharp shape of the nanogap densifies the electric field to maintain a stable current flow due to field migration. Even at 873 K, which is a significantly higher temperature than feasible for conventional semiconductor memory, the nonvolatility of the proposed memory allows stable ON and OFF currents, with fluctuations of less than or equal to 10%, to be maintained for longer than eight hours. An advantage of this nanogap scheme for high-temperature memory is its secure operation achieved through the assembly and disassembly of a Pt needle in a high electric field.

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confidence: 99%

Highly stable, extremely high-temperature, nonvolatile memory based on resistance switching in polycrystalline Pt nanogaps

Suga

Suzuki

Shinomura

et al. 2016

Sci Rep

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“…13,14 Earlier, we demonstrated a multilevel resistance switching and the possibility of increasing the bit capacity per cell. 15 Therefore, the nanogap switch based memory is scalable to ultrahigh densities. Switching from a low to high resistance (OFF) state involves the displacement of an electrode atom farther from its counterpart.…”

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confidence: 99%

“…The migration of atoms should be controlled with voltage pulses particularly, at high-speeds for commercial viability. Although the OFF state switching with ls pulse width was demonstrated 15 in the past, it is too slow in comparison to other resistive memories. The ON state switching was accomplished in the voltage sweep mode 12,16 only and the switching in pulse mode is not reported yet.…”

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confidence: 99%

Non-volatile high-speed resistance switching nanogap junction memory

Kumaragurubaran

Takahashi

Masuda

et al. 2011

Applied Physics Letters

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“…Those results are approaching the intrinsic value far from our previous works. ( [5], [8], [9]) Although the number of bits or nanogap elements measured is small, superiority of nanogap memory element has been confirmed in the programming speed, the element size and integrity to a conventional CMOS technology. Endurance cycles more than10 5 ,data retention, wide range operation under -80 150C[11] were already reported.…”

Section: Introductionmentioning

confidence: 98%

“…The current between the electrodes is due to electron tunneling. And the resistance corresponding to the gap distance was changed and controlled by applying voltage to the electrodes [5]. We have studied this phenomenon and applied for nonvolatile nanogap memory [8], because of its superior properties, i.e.…”

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confidence: 99%

4kb nonvolatile nanogap memory (NGpM) with 1 ns programming capability

Takahashi

Furuta

Masuda

et al. 2012

2012 IEEE Silicon Nanoelectronics Workshop (SNW)

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A 4k bits nonvolatile high-speed nanogap memory device was fabricated with a newly developed vertical nanogap structure and its memory characteristics were evaluated. The newly developed vertical nanogap structures realized controllable electrode gap and higher yield compared to the initial phase lateral type nanogap structure. The structures were integrated on a CMOS chip. The specially embedded measurement circuit revealed programming speed from a low resistance state to a high resistance state (from on to off state) to be 1 ns.Introduction One of the authors found that thin film metal electrodes with a gap less than 10 nm on an insulating substrate showed nonvolatile memory effect in vacuum [1]. Similar nanogap resistance change were widely observed for metals, such as Au, Pd, Pt, Ta [2], and even for Si [3] and carbon nanotubes [4] not only in vacuum but also in inert gases [10]. The current between the electrodes is due to electron tunneling. And the resistance corresponding to the gap distance was changed and controlled by applying voltage to the electrodes [5]. We have studied this phenomenon and applied for nonvolatile nanogap memory [8], because of its superior properties, i.e. high speed resistance switching, operation in a wide temperature range up to 200 C[1] and intrinsic high bit density. In this paper, results of integration of the nanogap memory (NGpM) on a CMOS LSI structure and evaluation of high speed switching capability using a specially embedded measurement circuit are reported.Fabrication NGpM is initially configured laterally on the insulating substrate as shown in Fig.1a, which is called as lateral type. It has been used to investigate the property and the mechanism of nanogap resistance change [1],[6], [7], however it is not suitable for memory array. We have developed various vertical type nanogap elements and finally adopted a trench type and a hole-in-line type each of which is shown in Fig.1b and 1c respectivly.[8] Using these types of nanogap element, a 4kb NGpM is integrated on a CMOS LSI in which transistors for each nanogap element selection, control circuits and the specially designed embedded measurement circuits were furnished. The technology of the CMOS LSI is 0.35 m high-voltage process of a foundry. Fabrication process on the chip is summarized in table 1. In this vertical type the gap distance between 1st and 2nd metal is determined by the spacer thickness, which is 10nm or less. The device size factor F is 40nm for hole-in-line type and 60nm for trench type. In the vertical type, the nanogap element is located at the cross point of upper and lower electrode, then 4F 2 is minimum size needed for a memory element. A nanogap element finer than 40nm also operates properly.[7] ProgrammingIn our previous work, it was very difficult to investigate the intrinsic programming speed of the nanogap elements, because of limitation of commercially available pulse generators with high-voltage high-speed drivability (10V, 10ns) and also an influence of the parasitic capacitance of lead p...

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Control of nanogap junction resistance by imposed pulse voltage

Cited by 19 publications

References 9 publications

Highly stable, extremely high-temperature, nonvolatile memory based on resistance switching in polycrystalline Pt nanogaps

Highly stable, extremely high-temperature, nonvolatile memory based on resistance switching in polycrystalline Pt nanogaps

Non-volatile high-speed resistance switching nanogap junction memory

4kb nonvolatile nanogap memory (NGpM) with 1 ns programming capability

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