Control of Polysilicon Emitter Bipolar Transistor Characteristics by Rapid Thermal or Furnace Anneal of the Polysilicon/Silicon Interface

Abstract

In this paper we report on the ability of rapid thermal annealing (1050C, 45s) and furnace annealing (900C, 30min) to partially break up the interfacial oxide in bipolar transistors with different oxide thicknesses at the polysilicon/silicon interface. We have obtained the different oxide thicknesses either by performing different ex situ cleans (RCA clean or RCA clean + HF dip) before Low Pressure Chemical Vapor Deposition (LPCVD) of polysilicon, or by using a cluster tool for polysilicon deposition with the ability to perform an in situ clean and then allowing the growth of different oxide thicknesses at the interface prior to polysilicon deposition. For the in situ cleaned devices, it is observed that after the interface anneal, the current gain increases with increasing oxide thicknesses, but with little penalty in terms of higher emitter resistance, Re. This indicates that by controllably increasing the interfacial oxide thickness and by subsequent annealing to partially break up the interfacial oxide, higher current gains can be obtained with little sacrifice in terms of higher Re.